Week 
Monday 
Wednesday 
Friday 

1 
March 
Introduction (I) 
March 
Boolean Algebra (II) 
April 
Realizing Boolean Logic
(III) 
April 
Canonical Forms (IV) 
April 
Logic Minimization (V)

April 
Logic Minimization (V)
(cont) 

April 
Logic Logic
Minimization (VI) 
April 
Logic Time Behavior (VII) 
April 
Mux and Decoder Logic (VIII) 

April 
Programmable Logic (IX) 
April 
Adders (X) 
April 
Adders (X) (cont) 

April 
Comb. Logic Examples (XI) 
April 
Sequential Logic (XII) 
April 
Sequential Logic (XII)
(cont) 

May 
Sequential Logic (XII)
(cont) 
May 
Registers, Counters, Memories
(Registers.pdf) 
May 
Processor Intro (Registers.pdf) 

May 
Sequential Verilog (XIII) 
May 
Finite State Machines Part I (XIV) 
May 
FSMs Part I, Verilog
for FSMs 

May 
Sequential Verilog Examples 
May 

May 

May 
Project Specification (XVI) 
May 
Design Example: RunLength Encoder 
May 
Design Example (cont): RunLength Decoder 

10 
May 
Memorial Day 
June 
FIFOs and Asynchronous Inputs 
June 
Final Exam Review and
Evaluations 


June 
Final Exam 

