CSE 370 Course Calendar for Spring 2010
(Subject to Change!)

Week

Monday

Wednesday

Friday

1
Lab 0

March
29

Introduction (I)
Reading: Ch. 1

March
31

Boolean Algebra (II)
Reading: Ch. 2.1 - 2.2

April
2

Realizing Boolean Logic (III)
Reading: Ch. 2.3, 4.1
Quiz 1 Solution

2
Lab 1
HW1

April
5

Canonical Forms (IV)
Reading: Ch. 2.4 - 2.5

April
7

Logic Minimization (V)
Reading: Ch. 2.6 - 2.7
Homework 1 due Solution

April
9

Logic Minimization (V) (cont)
Reading: Ch. 2.6 - 2.7
Quiz 2 Solution

3
Lab 2
HW2

April
12

Logic Logic Minimization (VI)

Reading: 3.1 - 3.2

April
14

Logic Time Behavior (VII)
Reading: Ch. 4.2
Homework 2 due Solution

April
16

Mux and Decoder Logic (VIII)
Reading: Ch. 3.5
Quiz 3 Solution

4
Lab 3
HW3

April
19

Programmable Logic (IX)
Reading: Ch. 4.2 4.3

April
21

Adders (X)
Reading: Appendix A.4, Ch. 5.6
Homework 3 due Solution

April
23

Adders (X) (cont)
Quiz 4 Solution

5
Lab 4
HW4

April
26

Comb. Logic Examples (XI)
Reading: Ch. 5.1 - 5.4

April
28

Sequential Logic (XII)
Reading: 6 (pp. 259-265, 275-281, 289-294)
Homework 4 due Solution

April
30

Sequential Logic (XII) (cont)
Reading: Ch. 7.1
Quiz 5 Solution

6
Lab 5
HW5

May
3

Sequential Logic (XII) (cont)
Reading: Ch. 7.1 7.2

May
5

Registers, Counters, Memories (Registers.pdf)
Reading: 7.2 7.3
Homework 5 due Solution

May
7

Processor Intro (Registers.pdf)
Reading: 7.2 7.3
Quiz 6 Solution

7
Lab 6
HW6

May
10

Sequential Verilog (XIII)
Reading: 7.2 7.3

May
12

Finite State Machines Part I (XIV)
Reading: 7.2 7.3, 8.2 8.4
Homework 6 due Solution

May
14

FSMs Part I, Verilog for FSMs
Reading: Ch. 8
Quiz 7 Solution

8
Lab 7
HW7

May
17

Sequential Verilog Examples

rotate example, register file example

May
19


Processor Design (x370)
Tug-of-War FSM example
Homework 7 due Solution

May
21

Dual and Single Ported Memories
Quiz 8 Solution

9
Lab 8
HW8 & 9

May
24

Project Specification (XVI)
(for Lab 8 and Lab 9)

Communicating FSMs example

May
26

Design Example: Run-Length Encoder
rle.v
, rletf.v
Homework 8 due Solution

May
28

Design Example (cont): Run-Length Decoder
rld.v
Quiz 9 Solution

10
Lab 9

May
31

Memorial Day

June
2

FIFOs and Asynchronous Inputs

June
4

Final Exam Review and Evaluations
SampleQuestions
Homework 9 due 5:30PM Solution
Lab 9 due 5:30 PM





June
9

Final Exam
8:30-10:20, EEB 045

 

 

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