CSE 370 Laboratory
Assignment
Designs in FPGAs
(Field Programmable Gate Array)
Assigned: Monday, May 3, 2010
Due: Beginning of Next Lab Section
Read the entire lab
assignment carefully before you begin working on it!
Objectives
In
this laboratory assignment you will work extensively with Verilog
and Active-HDL to design an 8-bit accumulator. When you have finished designing
the accumulator you will implement it on your FPGA to try it out. To help you
through this process we will guide you with design steps for each part of the
accumulator; however it will be your job to figure out how to put them together
properly and make it work on the FPGA. If you finish early, feel free to
explore the FPGA, you have over 18000 logic elements in the FPGA, more than you
will probably ever need for what we’re doing.
Before You Begin
- For this lab, it is strongly suggested that you create
a NEW design in your workspace. Call it: lab5. Typically we don’t enforce
this kind of organization, however good organization makes debugging
easier and it reduces the chance for errors.
- You will need to write a pinout
file (.qsf) file for your design, you can find
the list of FPGA pinouts here: Pinouts.
Designing with Verilog
You
will only be using a simple subset of Verilog for
this lab which uses assign
statements only to describe logic functions.
We will be giving you a module that implements a register which will be
your introduction to sequential logic in Verilog. But for now, you will not have to design
sequential logic. You may want to refer
to the Verilog notes in Lecture 9. Remember that Verilog
is a hardware description language. Although it may look like a programming
language, Verilog is used to describe what the
hardware does; Verilog programs don’t actually get
executed by the hardware like C or Java.
In this lab, each 7-segment display is driven by a 7-bit value: each bit drives
one of the segments on or off. Your
design will assign the appropriate values to these 7 bits based on a 4-bit
binary input. Although you could assign
each bit separately, it is a lot easier to declare the value as a bus, e.g.
wire [6:0] out;
and
then assign the value as a decimal value, e.g.:
out = 48;
or better yet in this case to assign it as a
binary value, e.g.:
out = 7’b0110000;
Both of these work, it’s a matter of style
which you choose. Note for binary
format, the rightmost digit is the least significant and the leftmost digit is
the most significant.
In this lab you will have to assign values based on the comparisons. To do
this, we use the ternary conditional operator which is the same as in C or
Java. For example, the assign statement:
out = ( X== 1 ) ? 48 : 0;
will
assign out the value 48 if X is equal to 1, otherwise it will assign the value
0. You can nest these ternaries inside each other as well, which you can use to
implement the analog of a case statement.
Here is an example Verilog program example.v that implements a full-adder
using conditional statements to describe the sum and carry functions as a truth
table.
Hexadecimal Display
Background Information:
Your
first task will be writing an “encoder” in Verilog to
display 4-bit binary values using the hexadecimal displays on the board. If you
look to the left side of the board above LEDR5-9 you should see 4 hexadecimal
displays. They are labeled HEX0, HEX1, HEX2, and HEX3. They are called HEX
because they are generally used to display the hexadecimal values 0, 1, 2, 3,
4, 5, 6, 7, 8, 9, A, b, C, d, E, F for a 4-bit binary number. If you recall, we
use hexadecimal values to represent 4-bit binary values. So for example, the
binary value 0001 would correspond with the hexadecimal value of 1, and the
binary value 1111 would correspond with the hexadecimal value of F.
With this background information you need to build a hexadecimal decoder that
takes in a 4-bit value and outputs a 7-bit value that drives the 7-segment
hexadecimal display. It is a 7-segment display because each of the 7 segments
in one hexadecimal display can be turned on and off. When you give it a high
value (1) it turns off, and when you give it a low value (0) it turns on (NOTE
THE INVERSION). Finally you need to know how the 7 segments in the display are numbered,
you can go to documentation here: Documentation
and look at page 30 and 31. There will be a nice picture that tells you how the
7-segments in the display are numbererd (Figure 4.7).
(You will need to get used to using
Documentation to find important information about the parts you are working
with.)
Tasks
- Your first task is to write the Verilog
module that converts a 4-bit input number to the 7-bit bus that drives the
7-segment display. Make sure your Verilog module
has a 4-bit input bus and a 7-bit output bus. Your seven outputs will each
be a function of your four inputs. Once you have made your Verilog module you can test it by writing a (.qsf) file which directs the 4 inputs to SW0-3, and the
7 outputs to HEX0, 0-6. Writing the (.qsf) for a
Verilog file is just like writing a (.qsf) for a Block Diagram file (.bde),
you have to assign pins to input and outputs. So in the case where you
have the following at the beginning of your Verilog
file:
module toHex
(
output [6:0] y,
input [3:0] x);
You will need to assign pins for in[0], in[1], in[2], in[3], out[0],
out[1], out[2], and out[3], etc. If you don’t understand this concept ask
your TA to come over and explain it to you in more detail. After writing
up your (.qsf) you should implement your design
onto your FPGA and then test your 4-bit to HEX encoder to make sure it
works. Go through all the values 1-15 and make sure the HEX displays the
correct value.
- Your next task is to download the accumulator we have
provided here for you: reg.v.
This accumulator is just an 8-bit register to which you will be adding or
subtracting input values. On each
positive edge of the clock, the register will sample the input and then
hold it. If reset is asserted when
the clock “ticks”, then the register is cleared to zero. Note that this is a synchronous reset. You
have to clock it when reset is high.
Now you should test your accumulator to figure out how it works.
Create a block diagram and add the accumulator and four 4-bit to hex
display encoders onto the block diagram. Create the following inputs and
outputs on your block diagram:
1. An 8-bit input bus that will be driven by SW0-7.
2. Two 1-bit wires that will be driven by KEY0 and KEY1 which will be used
for reset and clock.
3. A 1-bit wire that will be driven by SW9 which will be used for the addsub control input. (Which we will use later for
your 8 bit adder/subtractor)
4. Four 7-bit outputs that will be used to drive the HEX0-3 7-segment
displays.
You should hook up the 8-bit input that is driven by the switches to the
8-bit input on the accumulator. Also hook up the reset and clock signals
on the accumulator to the two inputs that will be driven by KEY0 and KEY1.
NOTE: Since the KEY switches active-low (that is, 1 when not pressed, and
0 when pressed) you need to put an inverter on the two KEY inputs. Now add four copies of your 4-bit to hex
converters to the block diagram. The first two will be connected to the
8-bit input of the accumulator, and the last two will be connected to the
8-bit output of the accumulator. Now you have four 4-bit to hex converters
with 7-bit outputs. Hook them up to the four 7-bit outputs you made
earlier.
Now you need to write a pin assignment file (.qsf)
for all of your inputs and outputs. When that is completed, synthesize and
implement your design onto the FPGA. Test to make sure that it is working
correctly. Does the value of the switches display on the HEX display? Does
the value saved inside the accumulator show on the HEX display as well?
When you feel it is all working call over your TA for the first check-off
.
- Your next task is to create an 8-bit adder/subtractor. In short, an 8 bit adder/subtractor is a module which takes in 8 bits for A, 8
bits for B, and a single control signal specifies whether the modules is
to add or subtract, and returns an 8 bit Sum. Write this 8-bit adder/subtractor up in Verilog. You
may use the built-in Verilog add and subtract
operators to implement this module.
Each time you add or subtract it. Negative numbers are stored but your 7-bit
segment display will only show HEX so you will need to read the negative as 2’s
complement.
- When you have completed the adder/subtractor,
you need to add it to the accumulator to implement a circuit that will will add or subtract the input value from the switches
to the value saved in the register. When you figure it out, wire it up
correctly in the block diagram and write the (.qsf)
file for your design. Synthesize and implement it onto the FPGA and test
it out. Does it work? If it does call over your TA for the second
check-off.
Lab
Demonstration/Turn-In Requirements
A TA
needs to "Check You Off" for each of the tasks listed below.
- Check off your working Hex Decoder connected to the
accumulator.
- Check off your working 8-bit accumulator.
Comments
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