CSE
370 Laboratory Assignment
A
Reaction Timer: Verilog State Machines, 7-segment displays, and BCD Decoders
(Oh my!)
Objectives
In this
laboratory assignment you will continue to work in Verilog and Active-HDL,
implementing a state machine to create a reaction timer. You will draw on work
done in previous lab and homework assignments, reinforcing the modularity of
Verilog code. You will then test your code using the provided test-fixtures to
confirm correctness before implementing the assignment on the DE-1 board to
show that it works.
Design Problem
In this lab you will build a simple reaction timer using a 4-digit display to display the user’s reaction time in milliseconds. This reaction timer uses two buttons, Reset and Start/Stop to measure the reaction time:
1. The user first presses the Reset button, which causes the timer to go into an idle mode. The 7-segment displays will show 0’s in this mode.
1. The user then presses the Start/Stop button.
2. Once the Start/Stop button is released, the timer waits for a “random” period of time and then turns on an LED. We will use a “wait” module to tell us when we have waited long enough by asserting a wait_done signal.
3. The user presses the Start/Stop button as quickly as possible.
4. The reaction time in milliseconds on the 4-digit 7-segment display. It will remain in this state until Reset is pressed again.
We will be using a Clock Divider that produces a 1KHz clock, so you can simply count clock cycles to measure the time in milliseconds.
The Design Hierarchy
This lab is to be implemented using the following structure:
lab7 (provided) -- which instantiates:
· clk_div_50000 (provided)
· reaction_timer (provided) which instantiates:
· controller (your state machine)
· decimal_counter (built from 4 of your 1-digit BCD counters from HW6)
· wait_counter (provided)
· display (built from 4 of your toHex modules from Lab 5)
**Note** You will not be creating any block diagrams when working on this lab. You must provide Verilog modules for each module instantiated by reaction_timer.v. Also note that you will likely have to instantiate other modules within some of these modules; in effect adding one more level to the layout above. If you are confused about the syntax of structural Verilog, look at the code provided in reaction_timer.v and lab7.v or ask a TA.
Before Lab
First, note that you do NOT have to design these modules before lab. However, it is important to understand what they should do. Before lab you are however expected to create a state diagram for the controller. To do this, first write down the set of inputs and outputs the controller needs to implement the reaction timer. The controller's outputs should control the other modules in the system; namely the counters. The controller's inputs should give it information about its state and next_state. Using these inputs, design the state diagram, which generates the appropriate outputs at the appropriate time. Make sure to label all states and transitions, and be sure that you have covered all cases so that there are no ambiguities. Please implement this state_machine as a Moore machine. Outputs should be defined within states and inputs should determine state transitions. You will need to have this state diagram checked off by the TA before you begin the rest of the lab. If you have not designed the state diagram before lab, you may not be able to finish this lab assignment in 3 hours.
Before You Begin
1. You need to come to lab with a prepared state diagram. Read through the lab and draw the state diagram for your state machine.
3. You will need to move your toHex module and 1-digit BCD Counter source files into this design. Add them to the design as existing files. Make sure you check the "Make a local copy" box.
Tasks
1. (Before
Lab) Please come to your lab session with the state diagram of the
state machine you will implement. Label all states and transitions. You may even want to write the Verilog that
corresponds to your state diagram.
Have
your TA check your state diagram.
3. In Lab 5 you created a module ‘toHex’ that took a 4-bit binary input and generated 7-bit output to drive a 7-segment display. In this lab you only need to output digits 0 – 9.
**Note**
The test fixture's '9' does not include the bottom segment of the seven segment
display. If your toHex module's '9'
does, all '9's will be replaced with x's in the test-fixture.
Have
your TA check off that the top level simulation produces no x’s in your output.
(Optional
Extra Credit) The design
statement does not specify what should happen if the user is so slow that the
counter overflows. For a small amount of
extra credit, you can decide to handle this case explicitly instead of just
letting the counter wrap around.
Document in your code what your circuit does in this case. Spiffier designs will get more credit.
1.
Our solution to the random wait will be to use a
counter, which, while not truly random, will be good enough. We create an 11-bit binary counter that uses
the 1KHz clock and runs continuously.
How often does this counter “roll over”?
A 1-bit output called wait_done that is turned on when the counter value
equals 0. This output will be used by
the state machine to start the reaction timer.
(Optional
Extra Credit) This counter works
ok, but it can output a done signal very quickly (0 time), which is not very
fun for the user. For a small amount of
extra credit, change this design so that the wait time is between 1 and 3
seconds with an average of 2 seconds.
2. You
are now ready to put the entire design together: the state machine, the
reaction counter, the 7-segment display drivers and the wait counter. We will provide a test fixture that you can
use to test the entire design. You must
get the simulation to work before compiling into hardware. Visually inspect the output of the simulation
to verify that your design counts correctly only when it should.
Have
your TA check that your simulation works correctly.
3. Once
your circuit passes simulation, create a pin-out file to configure the board
for the switches, keys, LEDs, and clock signals you need, then synthesize your
project and implement it on your DE-1 board.
Have
a TA check-off your working reaction timer.
Lab Demonstration/Turn-in Requirements
A TA needs to "Check You Off" for each of the tasks listed below.
1. State Diagram
2. 4-digit decimal counter simulation
3. Reaction timer simulation
4. Reaction timer hardware
5. (Optional) Extra credit