CSE370 Assignment 4


Distributed: April 21, 2010
Due: April 28, 2010



Reading:

  1. Katz/Borriello, Contemporary Logic Design 2e, Chapter 4, Section 4.2 and 4.3 (pp. 184-205)
  2. Katz/Borriello, Contemporary Logic Design 2e, Chapter 5 (pp. 221-253)

Exercises:

1.      Implement the following three functions three different ways, first using one ROM, then using one PLA and finally using one PAL.  For the PLA, try to minimize the number of AND gates you use.  Use the ROM and PLA/PAL worksheets to do this, but show all your work for how you get your results.

a)      f1(a,b,c,d) = m(8, 4, 12, 14, 13) + d(10, 6)

b)      f2(a,b,c,d) = m(10, 12, 14) + d(6)

c)      f3(a,b,c,d) = m(10, 4, 11, 13, 15) + d(9, 7)

2.      CLD-II, Chapter 5, problem 5.21  Give the value of all the signals in the multiplier array. You may just write the values on this copy of Figure 5.26.

a)      Assume that at time 0, all input values change from 0 to the values given in the problem.  At what time does the slowest output bit change?

b)      What is the worst-case delay for this multiplier?

3.      In this problem, you will implement and test a complete 16-bit carry-lookahead adder using Active-HDL.  You will find test fixtures for each of the components and the final circuit in the 370 course hw4 folder (courses\cse370\10sp\) and also in this ZIP file.  Make sure you use only components from the lib370 library.

a)      Design and test a 1-bit adder which has three inputs, A, B, Cin, and three outputs, Sum, P, and G, where P and G are the propagate and generate functions.  You may use either a schematic with gates, or a Verilog file with assign statements and Boolean equations.

b)      Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0].  (This 4-bit adder is just four independent copies of the 1-bit adder.)  You must use a schematic for this.

c)      Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG.  BlockP and BlockG are the block propagate and block generate functions. You may use either a schematic with gates, or a Verilog file with assign statements and Boolean equations.

d)     Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder.  You must use a schematic for this.

e)      What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?

f)       If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?


Rationale:

  • To practice describing logic block with Verilog.
  • To measure circuit performance for complex logic such as adders.
     

Comments to: cse370-webmaster@cs.washington.edu