| Week |
Monday |
Wednesday |
Friday |
1
Lab 1 |
3/30 |
Introduction
Readings: 1
|
4/1
HW 1
|
Number systems
(ppt, pdf)
Readings: Appendix A
|
4/3 |
Boolean algebra
(ppt, pdf)
Readings: 2.1 - 2.2
|
2
Lab 2 |
4/6 |
Logic gates, truth tables,
and canonical forms
(ppt, pdf)
Readings: 2.3 - 2.4.1
|
4/8
HW 2
|
NAND/NOR conversion,
Boolean cubes
(ppt, pdf)
Readings: 2.5 - 2.5.2, 3.2.3
Homework 1 due
|
4/10 |
Karnaugh maps
(ppt, pdf)
Readings: 2.4.2, 2.5.3, 3.1
|
3
Lab 3 |
4/13 |
Verilog
(ppt, pdf)
Readings: 3.6
|
4/15
HW 3
|
Logic minimization, multiplexers
(ppt, pdf)
Readings: 4.2 - 4.2.2
Homework 2 due
|
4/17 |
Demultiplexers, PLAs/PALs
(ppt, pdf)
Readings: 4.2.3
|
4
Lab 4 |
4/20 |
ROMS, multi-level logic
(ppt, pdf)
Readings: 2.6, 3.4.2
|
4/22
HW 4
|
Midterm Review
Homework 3 due
|
4/24 |
Midterm |
5
Lab 5 |
4/27 |
Timing, hazards
(ppt, pdf)
Readings: 3.5
|
4/29
HW 5
|
Adders
(ppt, pdf)
Readings: 5.6 - 5.6.2
Homework 4 due
|
5/1 |
Sequential logic,
state diagrams
(ppt, pdf)
Readings: 1.4
|
6
Lab 6 |
5/4 |
Flip-flops and latches
(ppt, pdf)
Readings: 6.1
|
5/6
HW 6
|
Registers and Counters
(ppt, pdf)
Readings: 6.3, 7.1
Homework 5 due
|
5/8 |
Timing
(ppt, pdf)
Readings: 6.2 - 6.2.4
|
7
Lab 7 |
5/11 |
FSM design,
Moore/Mealy machines
(ppt, pdf)
Reading: 7.2 - 7.3
|
5/13
HW 7
|
More Moore/Mealy machines
(ppt, pdf)
Reading: 7.3
Homework 6 due
|
5/15 |
FSM design examples
(ppt, pdf)
Reading: 7.4
|
8
Lab 8 |
5/18 |
Midterm Review |
5/20 |
Midterm |
5/22 |
State minimization
(ppt, pdf)
Reading: 8.1 - 8.1.1
|
9
Lab 9 |
5/25 |
NO CLASS |
5/27
HW 8
|
Minimization with implication charts
(ppt, pdf)
Reading: 8.1.2 - 8.1.4
Homework 7 due
|
5/29 |
State encoding and partitioning
(ppt, pdf)
Reading: 8.2 - 8.2.4, 8.3
|
| 10 |
6/1 |
Design example: Traffic light controller
(ppt, pdf)
|
6/3 |
Odds and ends
(ppt, pdf)
Homework 8 due
|
6/5 |
Final review
|
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