CSE 370: Introduction to Digital Design, Spring 2009

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Logic Design Tools We will be using Active-HDL from Aldec Inc. This tool combines schematics, the Verilog harware description language and simulation into one package. This tool will allow us to design at different levels of abstraction and interfaces to a variety of implementation tools for FPGAs and ASICs. We will be using the Aldec tools for CSE378, CSE467 and CSE477, so learning it in CSE370 will be valuable for future classes.   Version7 of Aldec is installed in the Baxter Laboratory and the other instructional labs. We will be giving you tutorials for learning Active-HDL. These will be sufficient for this class, but you may want to check out the online documentation as well. Several tutorials are available: Active-HDL Tutorial 0 Introduction to ActiveHDL (pdf version only) Active-HDL Tutorial 1 Creating and Simulating Simple Schematics (pdf version) Active-HDL Tutorial 2 Hierarchical Designs and Test Fixtures (pdf version) Active-HDL Tutorial 3 Introduction to Using Verilog in Active-HDL (pdf version) Active-HDL Tutorial 4 Describing FSMs in Verilog (pdf version) Portions of the CSE 370 Web may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited. The CSE 370 Web: © 1993-2009, Department of Computer Science and Engineering, University of Washington.