Course Description

CSE370 Introduction to Digital Design (4) Introductory course in digital logic and its specification and simulation. Boolean algebra, combinatorial circuits including arithmetic circuits and regular structures, sequential circuits including finite-state machines, use of programmable logic devices. Simulation and high-level specification techniques are emphasized. Offered: AWSp.

The department has an official syllabus description for CSE 370

Course Goals

Understanding of digital logic at the gate and switch level including both combinational and sequential logic elements.
Understanding of the clocking methodologies necessary to manage the flow of information and preservation of circuit state.
An appreciation for the specification methods used in designing digital logic and the basics of the compilation process that transforms these specifications into logic networks.
Facility with a complete set of tools for digital logic design with programmable logic devices as the implementation technology and the realization of medium-sized state machine controller and data paths using PLDs and discrete logic.
To begin to appreciate the difference between hardware and software implementations of a function and the advantages and disadvantages of each.
Understand “how” these concepts are used in the real world and “why” it is useful for us to know.

Topic List

1. Combinational logic basics

Binary/hex/decimal numbers
Ones and twos complement arithmetic
Truth tables
Boolean algebra
Basic logic gates
Schematic diagrams
Timing diagrams
De Morgan’s theorem
AND/OR to NAND/NOR logic conversion
K-maps (up to 4 variables), logic minimization, don’t cares
SOP, POS
Minterm and maxterm expansions (canonical, minimized)

2. Combinational logic applications

Combinational design

· Input/output encoding

· Truth table

· K-map

· Boolean equation

· Schematics

o Multiplexers/demultiplexers

o PLAs/PALs

o ROMs

o Adders

3. Sequential logic building blocks

Latches (R-S and D)
Flip-flops (D and T)
Latch and flip-flop timing (setup/hold time, prop delay)
Timing diagrams
Asynchronous inputs and metastability
Registers

4. Counters

Timing diagrams
Shift registers
Ring counters
State diagrams and state-transition tables
Counter design procedure

1. Draw a state diagram

2. Draw a state-transition table

3. Encode the next-state functions

4. Implement the design

Self-starting counters

5. Finite state machines

Timing diagrams (synchronous FSMs)
Moore versus Mealy versus synchronized Mealy
FSM design procedure

1. State diagram

2. State-transition table

3. State minimization

4. State encoding

5. Next-state logic minimization

6. Implement the design

State minimization
One-hot / output-oriented encoding
FSM design guidelines
Pipelining, retiming partitioning basics

Class Structure

1. Lectures: Attendance and participation of all of them is strongly encouraged.

2. Laboratory: There will be 9 weekly lab assignments (the last lab assignment spans 2 weeks). Although you'll be able to use the lab all week, attendance at one of the scheduled times is very important as that is when the TAs will be available. We will work hard to ensure that the laboratory assignments take no more than the three hour sessions to complete. You should attend the session for which you are registered. With permission of the TA, you can attend the other section in case of unusual circumstances.

3. Assignments: There will be 8 weekly homework assignments. They will be based on topics covered in lectures. There will be also reading assignments from the Contemporary Logic Design (2nd edition) text each week which is critical to keep up with the class materials.

4. Exams: There are two in-class midterms and one final exam during finals week.

Textbook

Contemporary Logic Design (2nd Edition) by Randy H. Katz and Gaetano Borriello. The text is available from the bookstore as well as online booksellers and used. Avoid the international edition, as it is not the same.

Class Policy

Grading

Your course grade will be computed as follows:

30% homework assignments

Homework assignments are due in class on the day they are due. Late assignments will only be accepted with prior arrangement

20% lab assignments

The lab grades are based on completion checked by the TAs. Don’t fall behind because each lab is worth more than 2% of your grades!

15% for each midterm (so 30% total)
20% final exam (cumulative but strong emphasis on materials after both midterms)

Collaboration

Unless specifically stated otherwise, we encourage collaboration on assignments, provided (1) you spend at least 15 minutes on each and every problem alone, before discussing its general concepts with others, (2) you only discuss general concepts or related examples - not the specifics of a problem on the assignment, and (3) you write up each and every problem in your own writing, using your own words, and understand the solution fully. Copying someone else's work is cheating (see below), as is copying the homework from another source (e.g., prior year's notes, etc.).

Cheating

Cheating is a very serious offense. If you are caught cheating, you can expect a failing grade and initiation of a cheating case in the University system. Basically, cheating is an insult to the instructor, to the department and major program, and most importantly, to you and your fellow students. If you feel that you are having a problem with the material, or don't have time to finish an assignment, or have any number of other reasons to cheat, then talk with the instructor. Just don't cheat.

To avoid creating situations where copying can arise, never e-mail or post your solution files in public directories. You can post general questions about interpretation and tool use but limit your comments to these categories. If in doubt about what might constitute cheating, send the instructor e-mail describing the situation.

Class Guidelines

Workload

We will try to ensure that the workload is typical for a four-credit course, namely, nine to twelve hours per week outside of the lectures. If we do not succeed, please let us know. Explain which parts of the course are causing you to spend too much time non-productively.

We have structured the course so that spending an hour or two per day will maximize your efficiency. You will work this way in the real world—you cannot cram a three-month design assignment into the last night—so you may as well work this way now. Plus, you will understand the material better. If you leave the homework for the day before it is due, then you will not have time to study for the exams, and you will not have time to ask questions when (not if) the software misbehaves.

Assignment

The homework assignments are generally due on Wednesdays in class (except when there is an exam or a holiday). The homework assignments will be distributed approximately one week before their due dates.

Your assignments must be neat and legible. We will not spend time trying to decipher messy work. We urge you to use the graphical and word processing tools that are readily available to you in all the labs in the department. Please make good use of the schematic diagram editor in the tools you'll be using to make neat circuit diagrams to include in your assignments.

Assignment problems will sometimes be graded on a random basis. To get full credit for an assignment, you must, of course, turn-in solutions for each assigned problem. Only a subset of the problems will actually be graded in detail. You will not know in advance which problems this will be - so make sure to do all of them.

Please review the assignment solutions carefully before questioning a grade with either the instructor or the teaching assistants.

Exams

We have two midterms and one final exam. Note their dates and times. Any difficulties with attending the exam times must be dealt with by prior arrangement with the instructor.

Software

Software tools frequently consume more time than they should. We have designed the assignments to get you up to speed gradually (over the period of a few weeks), but undoubtedly there will be some start-up cost (as with any new tool). Essentially, you are learning a new language, a compiler, and getting familiar with a process. Every tool imposes a certain model. Your frustration can be high until you assimilate that model and learn to use it effectively. Be sure to use the tutorials, and do not spend countless hours making no progress. Ask for help. Remember that these tools are written by engineers for engineers and will not necessarily conform to expectations you may have of consumer-oriented tools such as Word.

Portions of the CSE 370 Web may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited. The CSE 370 Web: © 1993-2009, Department of Computer Science and Engineering, University of Washington.