CSE 471: Computer Design and Organization - Autumn 2004
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Lectures
Branch Prediction
Pipelining Basics
(review)
Introduction to Out-of-Order Scheduling
Multiple Issue
Out-of-Order Execution
Register Renaming with a Physical Register File (R10000)
Reorder Buffer Implementation (Pentium Pro)
Precise Tomasulo Example
Cache Basics
Advanced Caching Techniques
Multithreaded Architectures
Multiprocessor Architectures
Cache Coherency
Directory-based Cache Coherency
Synchronization
Computer Science & Engineering
University of Washington
Box 352350
Seattle, WA 98195-2350
(206) 543-1695 voice, (206) 543-2969 FAX
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