Course Calendar     CSE 370   Autumn, 2009

Week	Monday		Wednesday		Friday
1			09/30	Introduction Readings: 1	10/02	Binary Number Systems Readings: Appendix A
2 Lab 1	10/05	Boolean Algebra Readings: 2.1 - 2.2	10/07 HW1	Logic gates and truth tables Readings: 2.3 - 2.4.1	10/09	Canonical Forms Readings: 2.3 - 2.4.1
3 Lab 2	10/12	Boolean cubes/Karnaugh Maps Readings: 2.5 - 2.5.2, 3.2.3	10/14 HW2	Karnaugh Maps/Logic minimization Readings: 2.4.2, 2.5.3, 3.1 Homework 1 due	10/16	Introduction to Verilog Reading :Verilog Reference
4 Lab 3	10/19	Multiplexers-DeMux Readings: 4.2 - 4.2.2	10/21 HW3	Multi-level logic Readings: 4.2.3 Homework 2 due	10/23	Review Readings: 2.6, 3.4.2
5 Lab 4	10/26	Exam 1 Exam 1 Solution	10/28 HW4	Structured logic implementation:PLAs,PALs	10/30	Adders Readings: 5.6 - 5.6.2 Homework 3 due
6 Lab 5	11/02	Introduction to FPGAs	11/04 HW5	Flip-flops Readings: 6.1	11/06	Sequential Verilog Reading :Verilog Reference Homework 4 due
7 Lab 6	11/09	State Diagrams Readings: 1.4	11/11 HW6	Veteran's Day	11/13	State Diagrams Readings: 6.3, 7.1 Homework 5 due
8 Lab 7	11/16	Clock Skew FSMs	11/18	Counter Design FSMs-2	11/20	Computer Organization I Reading: 7.2 - 7.3 Homework 6 due
9 Lab 8	11/23	Exam 2 Exam 2 Solution	11/25 HW7	Computer Organization II Reading: 7.4	11/27 Holiday	Thanksgiving Holiday
10 Lab 9	11/30	FSM Examples Reading: 8.1 - 8.1.1	12/02	Sequential examples Reading: 8.1.2 - 8.1.4 Homework 7 (First Part) due	12/04	Ant-Brain (extra credit) Reading: 8.2 - 8.2.4, 8.3
11	12/07	Sequential examples	12/09	State encoding-Partitioning Homework 7 (Complete Assignment) due	12/11	Review; evaluations; Final Exam Study Guide
	12/14	Final Exam: Monday, Dec. 14, 2009, 830-1020, MGH 241------------------- an extra lab check-off Thurs. Dec. 17, 1-4 p.m. in 003--Bruce

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