CSE370 Assignment 7

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Distributed: 25 Nov 2009
Due: 2 Dec 2009 (first part), 9 Dec 2009 (complete assignment)

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Reading:

1. Computer Organization Slides Part 1 and Part 2

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Introduction and set up:

In class you’ve talked about an introduction to computer organization. The examples you’ve seen were inspired by the MIPS family of microprocessors. In this assignment we will deal with a small and simple MIPS version implemented in ActiveHDL as Verilog code and schematics. This assignment will focus on the Controller of the CPU, but since that’s the CPU’s brain, orchestrating all functions, you will have to peek into all the other components as well.

In class you have seen state diagrams for CPU controllers that take multiple cycles to execute one instruction. In reality one would build a CPU like this, to assure that the critical path in the processor stays short and high clock frequencies can be reached. In our simple example all instructions take exactly one cycle and the CPU controller is purely combinational. That makes it easier for you, since you don’t have to deal with the trouble of getting a state machine right.

To set up your homework environment, please download the ActiveHDL implementation of our MIPS2001 CPU, unzip it and open the workspace mips2001.aws in ActiveHDL. The mips2000.bde schematic is your CPU, containing two memories (instruction memory and data memory, drawn in blue), one register file with 32 registers, an ALU to perform computation and additional logic to keep track of the program counter, multiplex input busses, … The mips2000_run.bde component connects your CPU to a clock generator, so that you can run simulations in ActiveHDL. (This is somewhat similar to the test fixtures you’ve seen before.)

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Exercises:

First part, due December 2:

1. Familiarize yourself with the components that you have seen in the lecture. Your task is to implement the controller of the CPU. So have a very thorough look at that component. Write down and hand in a list of all the controller inputs and outputs, give the information to what component they connect, what legal output values they can have and what control function is enabled by which value. (Hint: Look at the implementation and the comments in the other parts of the CPU.)
Example:

Port	Direction	Connects to	Value	Functionality
srcB	Out	ALU	0 1	Select RegB as second input Select Immediate as second input
…	…	…	…	…

2. Look at the imemory_alutest.v file. This is the CPUs instruction memory with a predefined program that does just a few operations (it exercises the ALU, the register file and the memory mapped I/O, but does no jumps!). It uses the ADDI, LUI, ALU-OR and SW instructions to load an immediate (= constant) value and perform memory mapped I/O to print a line stating “Debug print, value: 7”. Implement the control logic for those instructions in the MIPS controller by asserting the controller’s output signals accordingly. Make sure your program simulates correctly and prints the output. Hand in a printout of the simulation output.

Second part, due December 9:

3. Your goal is to determine the specific control signals needed for all of the instructions. Finish the skeleton code in controller.v, and replace all of the instances of x with the correct values. When your controller is working print and hand in your controller.v file. Here is a description of the instructions you need to implement.

Name	Enc	Abbr	R Behavior	PC Behav.
Arithmetic Op	Reg	ADD,SUB,etc	rd = rs op rt	PC++
Set on less than	Reg	SLT	rd = (rs < rt)? 1:0	PC++
Jump Register	Reg	JR	No change	PC=rs
I-Format Instructions
Load Word from Memory	Imm	LW	rt = MEM[rs+SE(immed)]	PC++
Store Word to Memory	Imm	SW	MEM[rs+SE(immed)] = rt	PC++
Add Immediate	Imm	ADDI	rt = rs + SE(immed[15:0])	PC++
Or Immediate	Imm	ORI	rt = rs | {ZERO[15:0],immed}	PC++
Load Upper Immed.	Imm	LUI	rt = immed[15:0],zeros[15:0]	PC++
Branch if equal	Imm	BEQ	No change	PC = PC+1+((rs == rt)? SE(immed) : 0)
J-Format Instructions
Jump	Jmp	J	No change	PC = {(PC+1)[31:26],Inst[25:0]}
Jump and Link	Jmp	JAL	r31=PC+1	PC = {(PC+1)[31:26],Inst[25:0]}

4. The file imemory_hanoi.v contains an implementation of the "Towers of Hanoi". It is quite high level MIPS assembler, using some of the general purpose registers to keep a stack pointer and similar things. You don’t have to worry too much about that file; the comments are intended for people with a knowledge of how C code gets compiled to assembler.
Replace your old ALU Test file with the Towers of Hanoi code. Right click on imemory_alutest.v and select “Exclude from compilation” and similarly include the Towers of Hanoi code. This code uses much more instructions than the first small example. If you get it to work, you can be quite sure that you’ve implemented your CPU correctly. Make sure your program simulates correctly and prints the output. Hand in a printout of the simulation output.
You can experiment with different input values for the number of discs used in the Towers of Hanoi. The number of discs is read from dmemory[254]. Note: This is a recursive implementation that stores info in dmem for each "call". Therefore, if you use too many discs, memory will overflow and things will stop working. You can fix this by increasing the size of memory in dmemory.v, and the number of bits of address used.

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Rationale:

• To get a first impression of CPU architecture
• Improve developing and debugging skills in Verilog using ActiveHDL

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Comments to: cse370-webmaster@cs.washington.edu