Course Calendar     CSE 370   Spring, 2007

Week	Monday		Wednesday		Friday
1 Lab 1 Reading:pp.1-9;Appendix A; pp. 33-46	03/26	Introduction Homework 1 distributed	03/28	Binary Number Systems	03/30	Boolean Algebra and theorums, gates
2 Lab 2 Reading:pp. 47-84	04/02	Logic Gates and Truth Tables Homework 2 distributed	04/04	Canonical Forms	04/06	Boolean cubes/Karnaugh Maps Quiz 1
3 Lab 3 Reading: pp. 67-83	04/09	Boolean cubes/Karnaugh Maps	04/11	Karnaugh Maps/Logic minimization Homework 3 distributed	04/13	Karnaugh Maps/Logic minimization
4 Lab 4 Reading:Verilog Reference; pp. 93-114, 139-145	04/16	Introduction to Verilog	04/18	Multi-level logic Homework 4 distributed	04/20	Multiplexers-DeMux Quiz 2
5 Lab 5 Reading:Chapter 4	04/23	Structured logic implementation: PLAs, PALs	04/25	Adders Homework 5 distributed	04/27	Sequential Logic
6 Lab 6 Reading: Chapter 5	04/30	Flip-flops; More Flip-Flops Quiz2- Take-home version (due 5/4/07)	05/02	Sequential Verilog Homework 6 distributed	05/04	State Diagrams Quiz 3
7 Lab 7 Reading:Chapter 6	05/07	Clock skew, Finite State Machines	05/09	Counter Design, FSMs-2 Homework 7 distributed	05/11	FSM Examples
8 Lab 8 Reading: Chapter 7	05/14	Computer Organization I	05/16	Computer Organization II Homework 8 distributed	05/18	Ant Brain (extra credit) Quiz 4 take-home version (due 5/21/07)
9 Lab 9 Reading:Chapter 8	05/21	State Minimization	05/23	Sequential Examples	05/25	State encoding-Partitioning
10 Reading:Chapters 9, 10	05/28 Holiday	Holiday- No Class	05/30	Introduction to FPGAs	06/01 last class	Review; evaluations Final Exam Study Guide
11	06/04	Final Exam: Monday, JUNE 4, 2007, 830-1020

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