CSE370 Assignment 6
Distributed: 2 May 2007
Due: 9 May 2007
Contemporary Logic Design 2e, Chapter 6 (pp. 259-298).
Okay folks, this
time the questions will be a little bit different from what you’re used
to, so I’d like to explain you why. I’ve looked through the stuff
that’s in the book and decided that I don’t really like most of it.
So I dug up the old things we had to do back home at the Universitšt
Karlsruhe (TH); so this week the assignment will not only do good for your
digital design skills but as well enhance international understanding ;-). I
thought it might be quite nice if I translate the questions for you, but as you
might remember, we Europeans use some different symbols for gates. So
I’ll give you a short explanation what means what, in your solutions you
can of course stick to the symbols you know.
<![endif]>Gate with an & sign in it: AND gate
<![endif]>Gate with ≥1 in it: OR gate
<![endif]>Gate with a 1 and negate output: NOT gate
- CLD-II, Chapter 6, problem
- The following picture shows
you three different kinds of either flip-flops or latches. You will find
explanations of more flip flop types in the textbook, where the JK flip
flop should be explained. The lowest one with a T input is a toggle flip
flop. It doesn’t have any set initial value (might be 0 or 1) and
changes it’s output value for every activation when the T input is
Look at the timing diagram for the inputs (by the way, “Takt” is the clock input), copy it to your
worksheet and add the signals for the three flip flop/latch outputs.
Assume that all output signals are initially 0 before the clock input
changes to 1 for the first time.
- This schematic shows a
circuit which is not combinational as those that you’ve seen before:
- Explain why this is no
- Introduce state
variables where necessary. That means for each feedback, break up the
feedback and introduce two new signal names (one output e.g. q and one
input e.g. q’ so that q’ = q) to model the feedback. Give the
Boolean expressions for the old and newly introduced outputs.
- Give the truth table
for the circuit. Which of the states are instable and to what state do
they traverse in case they occur?
- Draw a state diagram that
shows the states and transitions that can happen.
- What function does the
- The following circuit uses D
- What is the function
of this circuit? Have a close look at the case when x transitions from 0
to 1 in two different clock cycles and goes back to 0 some cycles later.
(Draw a timing diagram, if you can’t figure out what’s going
- If x has a short 1
spike (a 0-1-0 transition that’s shorter than a clock cycle) it
doesn’t work as expected. Modify the circuit so that this case is
covered as well. (Hint: you may need some flip-flops with asynchronous
inputs or some latches…)
- To see the difference between
combinational and sequential logic
- To understand how circuits
with feedback can be analyzed
- To understand the basic
building blocks of sequential circuits.
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