## CSE370 Assignment 6

### Distributed: 2 May 2007 Due: 9 May 2007

1. Katz/Borriello, Contemporary Logic Design 2e, Chapter 6 (pp. 259-298).

#### Exercises:

1. CLD-II, Chapter 6, problem 6.19.
2. The following picture shows you three different kinds of either flip-flops or latches. You will find explanations of more flip flop types in the textbook, where the JK flip flop should be explained. The lowest one with a T input is a toggle flip flop. It doesn’t have any set initial value (might be 0 or 1) and changes it’s output value for every activation when the T input is asserted. Look at the timing diagram for the inputs (by the way, “Takt” is the clock input), copy it to your worksheet and add the signals for the three flip flop/latch outputs. Assume that all output signals are initially 0 before the clock input changes to 1 for the first time.
3. This schematic shows a circuit which is not combinational as those that you’ve seen before: 1. Explain why this is no combinational circuit.
2. Introduce state variables where necessary. That means for each feedback, break up the feedback and introduce two new signal names (one output e.g. q and one input e.g. q’ so that q’ = q) to model the feedback. Give the Boolean expressions for the old and newly introduced outputs.
3. Give the truth table for the circuit. Which of the states are instable and to what state do they traverse in case they occur?
4. Draw a state diagram that shows the states and transitions that can happen.
5. What function does the circuit model?
4. The following circuit uses D flip flops: 1. What is the function of this circuit? Have a close look at the case when x transitions from 0 to 1 in two different clock cycles and goes back to 0 some cycles later. (Draw a timing diagram, if you can’t figure out what’s going on…)
2. If x has a short 1 spike (a 0-1-0 transition that’s shorter than a clock cycle) it doesn’t work as expected. Modify the circuit so that this case is covered as well. (Hint: you may need some flip-flops with asynchronous inputs or some latches…)

#### Rationale:

• To see the difference between combinational and sequential logic
• To understand how circuits with feedback can be analyzed
• To understand the basic building blocks of sequential circuits.