CSE370 Assignment 7
Distributed: 9 May 2007
Due: 16 May 2007
Reading:
- Katz/Borriello, Contemporary Logic Design 2e, Chapter 7 (pp. 307-347).
Introduction:
For this
homework you are asked to draw a couple of state diagrams. When you are doing this,
make sure to include a key that shows what the annotations in your diagram are
referring to. An example would be the following Mealy state diagram. The key on
the left tells you that the labels inside of the circles refer to your state
variables q0 and q1, the labels on the arrows give you
the input e and the output a:
Exercises:
- CLD-II, Chapter 7, problem 7.8.
- CLD-II, Chapter 7, problem
7.12 part (c).
Notes:
- In both cases your generated clock doesn’t have to run with the same frequency as the reference clock. Instead implement your solution so that it runs with fclk = fref/2.
- You may safely assume that each human that is going to press the STEP button will hold it down for longer than one clock period. In class you’ve heard about debouncing switches, but ignore that here or assume that the STEP button is already debounced.
- For your solution you should draw a state diagram first, explain with a few words what’s going on and then give a schematic for your implementation. Use D flip-flops to store your state.
Additional Notes:
There have been quite some questions about the clocking part in the office hour. First of all, I’d like to stress again that you should build two separate circuits! And to make your assignment more clear we will restrict it a bit, and only accept specific solutions. The textbook just forbids the generation of partial clock outputs. We will go for something stricter, namely that you decide once which clock pulses are allowable and then stick to your decision.
First, look at your reference Clock as an input. In the
diagram below it is denoted by the red waveform. Now your output clock should
operate with half the frequency of the reference clock. The green waveform
shows you the allowable transitions for the output clock (half of the
reference clock’s frequency, same duty cycle, edges aligned). We
won’t take all of them, since the output clock might either be turned of
(
The blue lines give a valid example for the step button. The first blue waveform might be an example of how the button gets presses. Now you have to decide which policy you’d like to implement. The upper waveform (Clk_out_3) shows you how your output clock should behave if you generate a clock pulse upon detection of the button press. The lower line (Clk_out_2) shows you how you would generate it, if you have a clock pulse as soon as you detect that the button was released.
Be careful, that you always stay consistent with your “green line”. In above diagram the rising edge of the generated clock can only be at ((odd number) x 100ns). So you shouldn’t generate a clock pulse that starts at e.g. 200ns once you detect that the button is pressed. (Of course in this picture you can take the opposite decision as well and have only clock pulses that start at ((even number) x 100ns). But then you should consistently stick to this. This decision would be represented by shifting your green waveform 100ns to the left or right.)
- CLD-II, Chapter 7, problem 7.18.
Notes: (apply for 7.19 as well)
In these questions you’re asked to count a number of thing. Usually when you’re drawing a state diagram you can have arrows that work for multiple inputs. So you label them either “00, 01” or maybe “0X” or “0-” if you don’t care for the second input variable. For this question an arrow with such a label would count as two arrows, since you could expand it to an arrow for the input “00” and one for the input “01”.
- CLD-II, Chapter 7, problem 7.19.
- CLD-II, Chapter 7, problem 7.27
Rationale:
- To get to know more about sequential logic, including legacy parts like counters.
- To understand Moore and Mealy state machines and the representation of a state diagram.
- Learning to design sequential circuits with a state machine approach