<![if !supportLists]>a) <![endif]>Design and test a 1-bit adder that has 3 inputs, A, B, Cin and three outputs: Sum, P, and G. P and G are the propagate and generate functions accordingly, and are defined as: G = AB, P = A XOR B. You may do this either with Verilog or a schematic.
<![if !supportLists]>b) <![endif]>Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.) You must use a schematic for this.
<![if !supportLists]>c) <![endif]>Design and test a 4-bit carry look-ahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions. You must use a schematic for this.
<![if !supportLists]>d) <![endif]>Using the 4-bit adder component and 4-bit carry look-ahead components, design and test a 16-bit carry look-ahead adder. You must use a schematic for this.
<![if !supportLists]>e) <![endif]>What is the size (# of gates) and delay (this time just the total # gates on the longest path) of your 16-bit carry look-ahead adder?
<![if !supportLists]>f) <![endif]>If you continued and made a 64-bit carry look-ahead adder using these components, what would be the size and delay of that circuit?
Turn-in your implementations/console outputs for part c,d and the answers to part e,f.
<![if !supportLists]>a) <![endif]>First describe how you would design a 16 Bit carry save adder. That means a component with the inputs A[15:0], B[15:0], C[15:0] and the outputs Sum[15:0], Carry[15:0]. (Either draw a schematic, or give a verbal description.)
<![if !supportLists]>b) <![endif]>To help you understand how your CSA works, describe how you’d build a component that adds three 16-Bit inputs A, B, C and produces the overall sum S. You have to use one CSA and as well a conventional 16-Bit CLA. (Remember that we don’t care about overflows! Draw a schematic for this.)
<![if !supportLists]>c) <![endif]>Now come up with a design that can add 8 16-Bit numbers together, using carry safe addition. You may use as many CSAs as you like, but only 1 CLA. The only restriction is that your design (which will most likely have a tree-like structure) has at most 5 levels, from the inputs to the outputs. (Draw as well a schematic for this. If you need some hints, try to look at this description of carry safe adders.)