f1(a,b,c,d) = ∑ m(8, 4, 12, 14, 13) + d(10, 6)
f2(a,b,c,d) = ∑ m(10, 12, 14) + d(6)
f3(a,b,c,d) = ∑ m(10, 4, 11, 13, 15) + d(9, 7)
a) First design a 2-bit comparator: This comparator compares two 2-bit numbers, A and B, on the input and produces two outputs, A=B and A<B. (A and B are unsigned numbers throughout this exercise.) Find the minimal 2-level circuit implementation for these two functions. Make a component for this comparator using Active-HDL. Use the text fixture compare2_tf.v to test your component. Print your schematic and console output from the simulation.
c) Now design an 8-bit comparator using four of your 2-bit comparators. Use the test fixture compare8_tf.v to test your component. Print your schematic and console output from the simulation.
d) Now design a 32-bit comparator using four of your 8-bit comparators. (Don't despair! How can you use the circuit you just designed? Feel free to cut and paste circuits between schematics, changing what you need to change.) Use the test fixture compare32_tf.v to test your component. Print your schematic and console output from the simulation.
e) Calculate the worst-case delay of your 32-bit comparator. (Express the delay as an expression using δANDx and δORx placeholders. For example (2 · δAND2 + δOR4) would be the delay of a path going through a 4 input OR gate and two 2 input AND gates. You can assume that a gate with more inputs has a higher delay than one with less inputs.)
f) What would be the size and delay of a 512-bit comparator?