CSE 467 Course Calendar for Winter 2011
(Subject to Change!)

Week	Monday				Wednesday			Friday
1 Lab 1 ModelSim		Jan 3	Overview and Combinational Logic Review	Jan 5		Combinational Logic Review Chapter 1 & 2	Jan 7		Combinational Logic Verilog Review Chapter 1, 2, 4:1-3
2 Lab 2 Reaction Timer		Jan 10	Sequential Logic and FSMs Verilog Review Chapter 3, 4	Jan 12		Sequential Logic and FSMs Verilog Review (cont) Test Fixtures Chapter 3, 4	Jan 14		Camera Pipeline Introduction Homework 1 Due
3 Lab 3 Image Filter		Jan 17	MLK Holiday	Jan 19		Registers and Timing Constraints Setup and hold time Clock skew Chapter 3	Jan 21		Asynchronous Interfaces and Metastability Chapter 3
4 Lab 4 Camera & Bayer2RGM		Jan 24	Asynchronous Interfaces Handshake protocols RS232 Protocol	Jan 26		Dual-Port Memories Synchronous FIFOs	Jan 28		Crossing Clock Domains Asynchronous FIFOs Source Synchronous Signaling Homework 2 Due
5 Lab 5 FIFOs		Jan 31	PLLs / Altera PLL display.v solution	Feb 2		bayer2rgb dataflow graph bayer2rgb.v solution Pipelining and Retiming Chapter 3.6	Feb 4		More Pipelining & Retiming
6 Lab 6 SRAM Interface		Feb 7	Scheduling, time-multiplexing Software Pipelining	Feb 9		SERDES Communication Homework 3 Due	Feb 11		Catchup/ Midterm Review
7 Lab 7 Project 1		Feb 14	Midterm	Feb 16		FPGA Architectures	Feb 18		FPGA Architectures Logic Factoring
8 Project 2		Feb 21	Presidents Day	Feb 23		Guest Lecture – FPGA CAD Tools (Place and Route) Larry McMurchie (Synopsys)	Feb 25		Guest Lecture – High Speed Signalling Vikram Jandhyala (EE) Project Milestone #1 Due
9 Project 3		Feb 27	Guest Lecture – FPGA Systems Andrew Putnam (Microsoft Research)	Mar 2		C-Slowing/Multi-Threading Homework 4 Due	Mar 4		Static/Dynamic memories Project Milestone #2 Due
10 Project 4		Mar 7	SDRAM memories	Mar 9		Reconfigurable Computing	Mar 11		Final Exam Review and Evaluations Goal for Class Project Completion
				Mar 16		Final Exam 8:30-10:20, EEB 045	Mar 17 Thursday		5:00 PM: Class Project Final Deadline

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