Schedule for CSE466, Autumn Quarter 2000
| Day | Lecture | Lab (by week)
Supporting Docs |
Homework assignment. Due on the day listed (May include Reading assignment) |
| M 1/7 | Course Intro and Introduction to FPGA platforms (Supplemental reading...Katz 10.3.4) | Lab 1, due 1/15 | |
| W 1/9 | HW Solution 1, State Machine Review | See 1/17 lecture notes for HW assignment due 1/9 | |
| F 1/11 | Synchronous v. Asynchronous Design | ||
| M 1/14 | Timing and Clock Skew | Lab 2, due 1/24 | HW 2 Asynchronous v. Synchronous State Diagrams Here are the solutions |
| W 1/16 | More Timing and Clock Skew | HW 3 Clock Skew Timing Analysis (Solutions in Lecture 1/16) | |
| F 1/18 | Verilog and Synthesis | ||
| M 1/21 | --- NO CLASS --- MLK Day | ||
| W 1/23 | Intro to Time Domain DSP | HW 4 Verilog Synthesis Examples | |
| F 1/25 | DJ Demo and Design Brainstorming | ||
| M 1/28 | Review (Lab1 example) | Lab 3, DSP Intro | |
| W 1/30 | Midterm 1 | ||
| F 2/1 | Midterm 1 and Time Domain DSP Overview
Cool Applets:
Decibel Demo, |
||
| M 2/3 | FIR Filters | HW 5 Read the chapter 5 from "DSP First ". Be prepared to answer one of two easy questions form this reading in class on Monday. | |
| W 2/5 | Pipelining, Retiming | Lab 4: Design Space Exploration for the DSL filter | HW 6: pipeline analysis |
| F 2/8 | SW Tools Group Presentations and Demos. Pipelining, Retiming Continued | ||
| M 2/10 | Filters Design Groups and Large Multiplier Group. C-Slowing and Retiming Technique | ||
| W 2/12 | Small Multiplier Report. Intro to Low Power Design | HW7: Pipelined System Design | |
| F 2/15 | FIR Filter Architecture (lost the notes) | ||
| M 2/17 | Holiday | ||
| W 2/19 | C-slowing and power/performance/space trade-off | ||
| F 2/22 | Midterm 2 | ||
| M 2/24 | Exam Review and Intro to the Graphics Pipeline | ||
| W2/26 | The
Graphics Pipeline (Great web overview by Univ. Leeds)
other references |
Lab 5: Independent Projects (with a little warm up) | |
| F 3/1 | Latch Based Design | Design the double buffering system using dual ported memories like the one in the Lab assignment. Use any muxes, gates, and state machines that you need to implement your system. The inputs would include pixel address and color data along with a signal to indicate when the graphics system has finished rendering the new scene | |
| M 3/4 | Latch Based Design | Homework: design of a parallelized rendering system that overcomes memory bottlenecks | |
| W 3/6 | Latch Based Timing Analysis | Latch Based Timing Analysis (See e-mail) | |
| F 3/8 | Test, Debug, and Verification | ||
| M 3/11 | Application: Dynamic Programming and DNA Sequence Analysis. | ||
| W 3/13 | Review | ||
| F 3/15 | Midterm 3 | ||
| M 3/20 | Demo and Pizza: 4:30 in 327 |
