Homework 7:

1. Using pipelining and retiming, maximize the throughput of this system. Show the new schematic and compute the latency and throughput of the new system. The bubbles represent combinational logic units. The numbers are the delays of each unit. You cannot split the combinational logic units into smaller pieces. (3pts)

2. Given the following constraints, design a pipelined implementation for the two filter system we are going to build in lab. (3pts)

•     You have room for 6 multipliers.
•     We want to build two 18  tap filters (one for audio and data channels)
•     System Clock rate (not sample rate)  is 25MHz
•     The multiplier Latency = 12 and Throughput = 25M multiplies/sec
•     Adder Latency = 2 and throughput = 25M adds/sec

    Draw a high level block diagram showing all of the major components of the system on one page.  Make sure you

1.     Explain what the controller has to do to make all of this work properly.
2.     Estimate the maximum sample rate that your architecture can support.