CSE 467 Lab 1
Due on 1/15/01 Beginning of Lab

Purpose

Become familiar with the tools. We will be using the Xilinx Foundation Series as the tool for digital system design in this class. We will start with some simple basics on how to open an archived Xilinx project, go through the design flow, and run a couple of simple simulations and make some measurements with the scope.

What You Are Given

You will download and open a Xilinx Foundation project archive that contains a starting schematic and simulation script template. Until the project is posted, you can refer to this schematic. In the schematic you will see a data register (DATA_REG) controlled by the button BTN1. The DATA_REG register controls the transfer of data from the seven switches SW0-SW7 to the multiplexer SEGMUX. The multiplexer drives both the anodes and cathodes of the four 7-segment LED displays found on the board. The project archive also contains a skeleton simulation script called lab1test.cmd that you will need to modify for your purposes. You can edit this file when you go to simulation mode in the Xilinx tools.

Your Job

Open the Xilinx project LAB1.ZIP and make a tour through the whole design process. Understand what the system does.

Identify the fundamental schematic building blocks in Xilinx (primitive elements like gates and buffers, logicBlox generated elements like the data registers [see tools-->logicBlox], and verilog modules).

Plug the board into the computer and download the bit pattern onto the board. (ATTENTION: YOU NEED TO HAVE YOUR WRISTWRAPS ON WHILE MANIPULATING THE BOARD.)

Test the functionality of the device.

Currently the project does not use all the eight switches. Change the project so that it uses all of them. To do this, you will have to check out the pin mapping by browsing to http://www.digilent.cc and you will need to edit the “UCF” constraint file.

After generating the design, check the estimate delay from clock to the A3 and A4 outputs. You find this information by consulting the “Implementation Report Files” in the “Reports” tab in Project Manager.

Use the scope to measure these delays and compare them with Xilinx’ estimates. The best way to get this measurement is to set the scope up for rising edge trigger on the output.

Run a simulation of the board using the LAB1.CMD script file. Understand the meaning of the script commands and the graphics obtained.

Change the script so that you change the data displayed from A5 to FF after 500 clock cycles.

Turn in

• An informal description of what the circuit does (specifically, what is going on in the SEGMUX and LED7SEG modules.
• A description of the changes needed for the circuit to use all eight switches.
• The modified LAB1.CMD file as specified above.
• You must demo your scope measurement for Larry our Andrei. Demos can be done at the beginning of lab next week.

Tool guide

The Foundation tool suite is an industrial strength tool for digital system design and prototyping. It includes design entry (schematic and HDL) simulation, and automated synthesis algorithms to implement your design on FPGAs. The results of simulation are available as simulation waveforms in a graphics window. 

In addition to this brief lab guide, there is also an on-line documentation and tutorial available under Xilinx Foundation in the start menu.

Start the Xilinx Foundation Tools from the start menu

Under the file menu choose "Restore Project" to restore the starting design from the lab1 archive, restore this design to a location on the desktop, Archive your own file server when you log off.  ALWAYS use Archive and Restore to move the design around. Never copy the working directory. In general, don’t fight the tools; they’ll wrestle you down. Go with the flow, do what they want, and they’ll stay friendly.

Schematic Based Design

To get started with schematics, select the Schematic Editor from the project manager to get a blank sheet for entering your design. You do not need to modify the design for this lab, but you will in the future so you might want to play around.

When entering your design observe the following rules (this has already been done for you for this project).

All input pins have to go through an IPAD then an IBUF.

All output pins have to go through an OPAD then an OBUF.

For system clock signal, use a BUFG instead of a IBUF.

These could be found in the Symbols Tool Box.

Verifying your Design

Simulate your design using the Logic Simulator. Select Functional Simulation from your project manager. Select Tools->Script Editor and choose "empty script" to edit your simulation script (LAB1.CMD file).  To start simulation, select File->Run Script File and choose a .cmd file. See here for an example simulation script that that you can start with (lab1test.cmd)

You will notice from the waveform that everything happens right at the clock edge. No delays are incorporated into the simulation. Signal delays could be simulated after implementation of design by using the Timing Simulation. (The Timing Simulation uses the same test script as the Functional Simulation.) Not necessary in Lab 1.

Here are some simulator hints:

· File/Run Script runs the script and updates the waveform display

· Tools/Edit Script lets you edit the script.

· If you change your schematic, close the simulator and start it again (there is probably an easier way to reload, let us know if you figure it out).

Testing your design

Connect the digilab board to the PC via the parallel cable. From the XILINX design manager, choose tools->device programming->hardware debugger. Set up the hardware debugger to use the parallel cable then download the bit file. When the device is programmed you should be able to flip switches, press buttons and see the display change appropriately.