CSE 467 Lab 4
Due on 02/26/02 Beginning of Lab
Design a
DSP system as a team. Collaborate with other teams in completing a project.
Make engineering tradeoffs between conflicting goals, modular design, teamwork.
High performance digital system design.
You can
use anything you want from the previous lab assignment.
You are
to design a splitter that discriminates two signals in disjoint frequency
bands. In other words, you will build a device that takes a high-bandwidth
signal and separates it into two signals – one in the 0-3 KHz band, and one
above 3 KHz.
This
technique is the basis of all modern telecommunication devices. It allows
mixing several distinct signals on the same wire/optical fiber.
The input
will be a wave that contains a mix of signals. For example, a simple test
signal could be 1 KHz sine wave mixed with an 6 KHz sine wave. Your task is to
separate the combined signal into to separate outputs. A more difficult test
case would be a 2.8KHz sine wave mixed with a 4KHz sine wave. The sample rate
of our system will stay at 16KHz, and we won’t worry about any input signals
above 7KHz.
System
requirements
The audio channel low pass
filter cutoff (-3dB attenuation) is as close to 3KHz as possible without going
over. See below for dB tutorial.
The goal is to minimize the high
pass filter cutoff (-3dB attenuation) such that the crossover between the two
filters is equal to or lower than –15dB. (see below for a tutorial on dB). A
lower cutoff means more bandwidth for your data channel so it gives you a
"competitive edge".
The
project will consist of three major phases: design space exploration,
architecture design, and implementation.
Design
Space Exploration. We will have three groups of four work on the two sub-problems in
this phase. These groups might want to communicate to avoid duplication of
work. Everyone’s results will be made available for the second phase.
1.
Multiplier Architecture. As you saw in the class, filtering is
addition and multiplication-intensive. We can’t always get away with shifting.
We need to look into what we can afford with our 300,000 gate FPGA.. The
question is, how many multiply-add operations can we do between samples
(running at 16KHz). There are three major multiplier architectures to consider:
1.
Pipelined (fastest and biggest)
2.
Combination (medium)
3.
Sequential shift and add (slow and small)
The teams working on this problem should try to map out these
cost/performance trade-offs, and should also consider a few different bit
widths widths. 10 bit and 12bit.
2.
Filter design. The one limitation of the filter design applet is that the
coefficients are very high precision. If we round them off to 10 or 12 bits,
how good is the resulting filter? This team can use excel or write their own
programs to compute the actual frequency response of the fixed point bit-width
limited system (basically simulate the filter). These teams should produce coefficients and frequency responses
for sets of coefficients with different numbers of taps.
Architecture
Phase:
Determine how we can effectively utilize a limited number of physical
multipliers and adders to implement two independent filters with sufficient
number of taps to achieve our goal.
Implementation: After you’ve done
a good job of the first two steps, this will be easy.
For (1),
produce and present charts and graphs showing the various time and space
trade-offs for multipliers and adders.
Your deliverables are Verilog modules for various different
implementations that we can all use in the next phase.
For (2),
produce and present filter design trade-offs with respect to computational
requirements versus filter quality. You
should show the simulated frequency response for a variety of filter designs.
Your deliverables are sets of coefficients and the software tools.
About
Decibels (dB)
Let IN be
the amplitude of the input signal (sine wave) and OUT be the amplitude of the
output sine wave. If
IN == OUT
then IN/OUT = 1 and you have 0dB attenuation.
If OUT/IN
= .7 you have 30% attenuation, which is –3dB.
To get dB from OUT/IN use this formula
A (in dB)
= 20*log(OUT/IN); // log is base 10
-15dB
(our crossover limit) the attenuation is
OUT/IN = 10^(-15/20)
= .17 or 83% reduction in amplitude. A
sine wave at the crossover frequency would be 83% attenuated.
Just for
grins a –100dB attenuation corresponds to a OUT/IN ration of .0001.