Problem 1: Draw the state machine representation of the following Verilog model (10pts).

module m(out, clk, data);

input clk, data;

output out;

always @(clk or data)

if (clk) out = data;

endmodule

For which edge of the clock (rising or falling) is input data subject to setup and hold constraints…why?

Problem 2: Draw the functional timing diagram of the following Verilog model given the input waveforms below. Note: inputs are synchronous. (20pts)

module mutex(grantA, grantB, reqA, reqB, clk);

input clk, reqA, reqB;

output grantA, grantB;

reg state;

always @(posedge clk) begin

if (reqB & ((state == `PRIORITYB) | ~reqA) ) state <= `PRIORITYB;

else state <= `PRIORITYA;

end

assign grantA = reqA & (state == `PIORITYA);

assign grantB = (state == `PRIORITYB);

endmodule

Problem 3: Write a Verilog description for the following circuit with input A and output Y (5pts).