Course Calendar CSE 370 Winter, 2008

Week	Monday		Wednesday		Friday
1 Lab 1	01/07	Introduction	01/09	Binary Number Systems *Homework 1 distributed*	01/11	Boolean Algebra and theorums, gates
2 Lab 2	01/14	Logic Gates and Truth Tables	01/16	Canonical Forms Homework 2 distributed	01/18	Boolean cubes/Karnaugh Maps Quiz 1
3 Lab 3	01/21	Holiday- No Class Reading:Verilog Reference	01/23	Introduction to Verilog Homework 3 distributed	01/25	Karnaugh Maps/Logic minimization
4 Lab 4	01/28	Multiplexers-DeMux	01/30	Multi-level logic Homework 4 distributed	02/01	Structured logic implementation:PLAs,PALs Quiz 2
5 Lab 5	02/04	Adders	02/07	Introduction to FPGAs Homework 5 distributed	02/09	no class
6 Lab 6	02/11	Flip-flops	02/13	Sequential Verilog Homework 6 distributed	02/15	State Diagrams Quiz 3
7 Lab 7	02/18	Holiday- No Class	02/20	Clock skew, Finite State Machines Homework 7 distributed	02/22	Counter Design Quiz 3 Takehome version due in class 2/27
8 Lab 8	02/25	Computer Organization I	02/27	Computer Organization II Homework 8 distributed	02/29	FSM Examples
9 Lab 9	03/03	FSMs-2	03/05	State Minimization	03/07	Sequential Examples Quiz 4
10	03/10	Ant Brain Project (extra credit)	03/12	State encoding-Partitioning	03/14 last class	Review; evaluations; Final Exam Study Guide
11			03/19	Final Exam: Wednesday, MARCH 19, 2008, 2:30-4:20 EE 037