CSE 378 Component Library

 

We built a set of verilog components that are useful for constructing your MIPS processor. Get the library here.  This link points to an archived Active-HDL design named lib378. You should restore this into an Active-HDL workspace. 

Download the updated Library!!!

To install the library, unzip the file to a convenient location. Then, in ActiveHDL, do the following:

  1. Go to File->Open, and browse to the directory where you unzipped the library.
  2. open the file named lib378.adf
    You should now have a design called "lib378"
  3. Make the lib378 design active using Right-Click->Set as Active Design
  4. Right-Click on the file "update_lib378.do" and select Execute
    This is a macro that cleans out the library, recompiles the files, and restores the read-only status of the library.
After you complete this portion, the library lib378.lib has been updated from the included source files. Now open the Libraries window, right click and select "Attach Library...", and select the .lib file in the newly created lib378 folder. Once this is done, right click on the library, and select "Add to Symbols Toolbox", then right click again, and select "Make Global".

Registers:
 
Component Description
register basic register with initial value
register_r register w/ reset signal
register_re register_r w/ clock enable (Load Signal)
 

Multiplexors:
 
Component Description
mux2_to_1 arbitrary width 2:1 multiplexor
mux4_to_1 arbitrary width 4:1 multiplexor
 

Arithmetic Units:
 
Component Description
adder arbitrary width 2 input adder
MIPSALU basic ALU
MIPSALU_2 more featured ALU
 

Wire Units:
 
Component Description
shiftLeft simple left shift
signEx basic sign extender
extender more general controllable extender

Memories:
 
Component Description
ROM256x32 instruction memory
ram_control write_controller used by ram16b_s36_wb  (used internally)
ram16b_s36_wb 8kB memory sync-write, byte addressable / byte writeable (DON'T USE FOR LAB1)
Ram256x32_sw_ar_wb 256 word memory, supports write byte, half-word, and word.  USE FOR LAB1
Memory_Toplevel Top level memory system for pipelined processors
MMU Routing for instruction and data requests based on addresses provided.

Misc:
 
Component Description
clockgen clock and local reset generator
constant represent a constant

Control:
 
Component Description
ALUControl controller for MIPSALU
ALUControl2 controller for MIPSALU_2

IO Devices:
 
Component Description
IOController Controller for up to 4 I/O Devices
MemoryMappedSerial Serial IO Device
MemoryMappedIO Controls the LEDs and reports on button statuses