Register Units
This page describes the included registers / registerfile in
greater detail.
Module: register
The register is the most basic sequential
element and this version is very simple. The actual implementation depends
on the ovi_unisim library. If you use this register you will be able to
specify an initial value for the register.
Parameters:
|
| |
| Name |
Default |
Description |
| EDGE |
1'b1 |
1'b1 = posedge triggered, 1'b0 =
negedge triggered |
| INIT |
32'h0 |
initial value at GSR. No WIDTH check |
| WIDTH |
32 |
bit width of D and Q |
|
|
| |
Port Description:
|
| |
| Name |
Dir |
Width |
Description |
D |
In |
WIDTH |
input value |
CLK |
In |
1 |
clock signal |
Q |
Out |
WIDTH |
stored value |
|
|
| |
|
|
| |
Notes:
|
| |
-
This symbol has a hidden CLK pin.
Use a global wire to connect to the CLK.
-
There must be a glbl.GSR signal defined to use this component
|
|
|
Module: register_r
This is a register with a reset signal. You
may choose synchronous or asynchronous reset using the SYNC_R parameter. The actual implementation depends
on the ovi_unisim library. If you use this register you will be able to
specify an initial value for the register.
Parameters:
|
| |
| Name |
Default |
Description |
| EDGE |
1'b1 |
1'b1 = posedge triggered, 1'b0 =
negedge triggered |
| INIT |
32'h0 |
initial value at GSR. No WIDTH check |
| SYNC_R |
1'b1 |
1'b1 = synchronous, 1'b0 =
asynchronous |
| WIDTH |
32 |
bit width of D and Q |
|
|
| |
Port Description:
|
| |
| Name |
Dir |
Width |
Description |
D |
In |
WIDTH |
input value |
CLK |
In |
1 |
clock signal |
RESET |
In |
1 |
reset signal (Active High) |
Q |
Out |
WIDTH |
stored value |
|
|
| |
|
|
| |
Notes:
|
| |
-
This symbol has a hidden CLK pin.
Use a global wire to connect to the CLK.
-
There must be a glbl.GSR signal defined to use this component
|
|
|
Module: register_re
This is extends register_r by the
addition of a clock enable input. In other words, the register only updates when
LD is high and the correct edge occurs. You
may choose synchronous or asynchronous reset using the SYNC_R parameter. The actual implementation depends
on the ovi_unisim library. If you use this register you will be able to
specify an initial value for the register.
Parameters:
|
| |
| Name |
Default |
Description |
| EDGE |
1'b1 |
1'b1 = posedge triggered, 1'b0 =
negedge triggered |
| INIT |
32'h0 |
initial value at GSR. No WIDTH check |
| SYNC_R |
1'b1 |
1'b1 = synchronous, 1'b0 =
asynchronous |
| WIDTH |
32 |
bit width of D and Q |
|
|
| |
Port Description:
|
| |
| Name |
Dir |
Width |
Description |
D |
In |
WIDTH |
input value |
CLK |
In |
1 |
clock signal |
LD |
In |
1 |
clock enable signal |
RESET |
In |
1 |
reset signal (Active High) |
Q |
Out |
WIDTH |
stored value |
|
|
| |
|
|
| |
Notes:
|
| |
-
This symbol has a hidden CLK pin.
Use a global wire to connect to the CLK.
-
There must be a glbl.GSR signal defined to use this component
|
|
|
Module: registerfile
This component represents that standard
MIPS register file. It contains 32 32-bit registers, 2 read ports, and 1
write port. Address 0 is always the value 0 for reading, and writing to
register 0 is ignored.
|
|
| |
Port Description:
|
| |
| Name
| Dir
| Width
| Description
|
| Read1 |
In |
5 |
specify register to supply Data1 |
| Read2 |
In |
5 |
specify register to supply Data2 |
| WriteReg |
In |
5 |
specify register to write into |
| WriteData |
In |
32 |
Data to write into register file |
| RegWrite |
In |
1 |
write signal for register file |
| CLK |
In |
1 |
clock signal |
| Data1 |
Out |
32 |
output value in register READ1 |
| Data2 |
Out |
32 |
output value in register READ2 |
|
|
| |
|
|
| |
Notes:
|
| |
-
This symbol has a hidden CLK pin.
Use a global wire to connect to the CLK.
|
|
|
