Multiplexers
Multiplexers are heavily used in computer architecture, but are
basically simple devices. You'd have no trouble writing your own versions. The
advantage of using these comes from the symbols. We designed the symbols
to look like the multiplexers in the textbook, and to take up minimal screen
real estate.
Module: mux2_to_1_top, mux2_to_1_bot
These are simple 2:1 multiplexers of
arbitrary width. To make schematics easier to read we provide two symbols
that both have the same implementation. The module mux2_to_1_top has its sel
input at the top, and the cleverly named mux2_to_1_bot has its sel input at the bottom.
Parameters:
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| Name |
Default |
Description |
| WIDTH |
32 |
bit width of inputs and outputs |
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Port Description:
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| Name |
Dir |
Width |
Description |
in0 |
In |
WIDTH |
input selected when sel = 0 |
in1 |
In |
WIDTH |
input selected when sel = 1 |
sel |
In |
1 |
selects between in0 and in1 |
out |
Out |
WIDTH |
output of the multiplexer |
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Symbols:
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The symbols for both variations are shown below. These are included if you want to do things in a block diagram. If you're
writing Verilog, it's probably easier to use the ? operator.
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Module: mux4_to_1_top, mux4_to_1_bot
These are 4:1 multiplexers of
arbitrary width. To make schematics easier to read we provide two symbols
that both have the same implementation. The module mux4_to_1_top has its sel
input at the top, and the cleverly named mux4_to_1_bot has its sel input at the bottom.
Parameters:
|
| |
| Name |
Default |
Description |
| WIDTH |
32 |
bit width of inputs and outputs |
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| |
Port Description:
|
| |
| Name |
Dir |
Width |
Description |
in0 |
In |
WIDTH |
input selected when sel = 0 |
in1 |
In |
WIDTH |
input selected when sel = 1 |
sel |
In |
1 |
selects between in0 and in1 |
out |
Out |
WIDTH |
output of the multiplexer |
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Symbols:
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The symbols for both variations are shown below. These are included for use in block diagrams. If you're writing Verilog, the two modules are completely interchangeable.
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