Arithmetic Components
The center of the computer is the Arithmetic and Logic Unit, but
we also provide a simple adder component for use in computing branches and
offsets.
Module: Adder
Simple unsigned adder of arbitrary size. No
overflow checking
Parameters:
|
|
Name |
Default |
Description |
WIDTH |
32 |
bit width of inputs and outputs |
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Port Description:
|
|
Name |
Dir |
Width |
Description |
inA |
In |
WIDTH |
one input for the addition |
inB |
In |
WIDTH |
second input for the addition |
out |
Out |
WIDTH |
out = inA + inB |
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Module: MIPSALU
This is the most basic implementation of the
ALU. It has only the most basic operations and no support for signed operations
of overflow checking.
Parameters:
|
|
Name |
Default |
Description |
AND |
0 |
control code for logical AND |
OR |
1 |
control code for logical OR |
ADD |
2 |
control code for Addition |
SUB |
6 |
control code for subtraction |
SLT |
7 |
control code for set on less
than |
NOR |
12 |
control code for logical NOR |
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|
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Port Description:
|
|
Name |
Dir |
Width |
Description |
A |
In |
32 |
left hand operand |
B |
In |
32 |
right hand operand |
ALUctl |
In |
4 |
determine which operation to
perform |
ALUOut |
Out |
32 |
result of the operation |
Zero |
Out |
1 |
(ALUOut == 0)? 1 : 0 |
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Module: MIPSALU_2
This is a more complex ALU that supports the
full complement of arithmetic and logical operations of both signed and unsigned
varieties. In general, the only difference between signed and unsigned
operations is the overflow checking. Signed operations perform overflow
checking, while unsigned operations do not. The lone exception is the Set
on Less Than (SLT) operation. Consider the following case:
SLTI SLTIU
|
$t0, $0, 0xFFFF $t1, $0, 0xFFFF
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# $t0 = 0. SignExt(0xFFFF) = -1 (2's complement) # $t1 = 1. SignExt(0xFFFF) = 2^32-1 (unsigned)
|
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This happens because the unsigned version compares the numbers
as unsigned numbers, while the signed version treats them as 2's complements
numbers. It's worth noting that SLTIU still performs sign extension on its
immediate.
Note: Does not implement any shift operations.
Parameters:
|
|
Name |
Default |
Description |
AND |
0 |
control code for logical AND |
OR |
1 |
control code for logical OR |
ADD |
2 |
control code for Addition |
ADDU |
3 |
control code for unsigned
addition |
SUBU |
4 |
control code for unsigned
subtraction |
SUB |
6 |
control code for subtraction |
SLT |
7 |
compare A and B as 2's
complement numbers |
SLTU |
8 |
compare A and B as unsigned
numbers |
XOR |
9 |
control code for XOR |
NOR |
12 |
control code for logical NOR |
|
|
|
Port Description:
|
|
Name |
Dir |
Width |
Description |
A |
In |
32 |
left hand operand |
B |
In |
32 |
right hand operand |
ALUctl |
In |
4 |
determine which operation to
perform |
ALUOut |
Out |
32 |
result of the operation |
Zero |
Out |
1 |
(ALUOut == 0)? 1 : 0 |
Overflow |
Out |
1 |
Overflow status of
signed operations |
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