CSE548: Computer Systems Architecture

1/7 Intro & Overview None
Slides
1/9 von Neumann Execution Model

(this looks like a lot but it really isn't)

Pre-von Neumann
ENIAC
More ENIAC

von Neumann
EDVAC
EDSAC
More EDAC

Optional reading:
Another view
Original von Neumann report
Rahul
Slides
1/14 Dataflow

A Preliminary Architecture for a Basic Dataflow Architecture
Two Fundamental Limits on Dataflow Multiprocessing
WaveScalar
Dan
Slides
1/16 Memory

Directions in Memory Interfaces
Raphael
Slides
1/21 Holiday
1/23 Class canceled - Work on projects!!!
1/28 An Efficient Algorithm for Exploiting Multiple Arithmetic Units
HPSm, a high performance restricted data flow architecture having minimal functionality
Jaylen
Slides
1/30 Very Long Instruction Word Architectures & Retrospective
A Design Space Evaluation of Grid Processor Architectures
Thierry
Slides
2/4 An Analysys of Correlation and Predictability
The Microrachitecture of the Pentium 4 Processor
Optional but highly recommended: A Study of Prediction Strategies, Retrospective
Optional: Dynamic Branch Prediction with Perceptrons
Stuart
Slides
2/6 Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
Prefetching using Markov Predictors
Robert
Slides
2/11 A Primer on Memory Consistency and Cache CoherencePages 1 - 6 (skim/skip), Pages 9 - 15, Pages 17-32, Pages 37-47 (It looks like a lot, but the font is big)
Cyrus
Slides
2/13 A Primer on Memory Consistency and Cache CoherencePages 99 - 119, Pages 133-137, Pages 139 - 153, Pages 169-170
Token Coherence: Decoupling Performance and Correctness
Rahul
Slides
2/18 Holiday
2/25 Power - Part 1
Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
Optimizing Pipelines for Power and Performance
Raphael
Slides
2/27 Power - Part 2
GreenDroid: Exploring the Next Evolution in Smartphone Application Processors (Read up to the "Green Droid" Architecture section on Page 114)
Dark Silicon and the End of Multicore Scaling
Dan
Slides
3/4 MTA
Exploiting heterogeneous parallelism on a multithreaded multiprocessor
Crunching Large Graphs with Commodity Processors
Stuart
Slides
3/6 Transactional Memory
"Transactional memory: Architectural support for lock-free data structures
Virtualizing Transactional Memory
Transactional Synchronization in Haswell
Thierry
Slides
3/11 GPUs
NVidia Tesla: A Unified Graphics and Computing Architecture
GPUs and the Future of Parallel Computing
Cyrus & Jaylen
Slides & Slides
A zip file with the lecture slides for the semester.
Privacy policy and terms of use