Interleaving (introducing parallelism at the DRAM level)
Memory is organized in banks
- Bank i stores all words at address j modulo i
- All banks can read a word in parallel ; Number of banks should match the L2 block size
- Bus does not need to be wider (buffer in the DRAM bank)
- Writes to individual banks for different addresses can proceed without waiting for the preceding write to finish
- Number of banks limited by increasing chip capacity
- With 1M x 1 bit chips, it takes 64 x 8 = 512 chips to get 64 MB (easy to put 16 banks of 32 chips)
- With 16 M x 1 chips, it takes only 32 chips (only one bank)
- More parallelism in using 4M x 4 chips (32 chips in 4 banks)