How to improve main memory bandwidth

• It’s easier to improve on bandwidth than on latency

• Sending address:can’t be improved (and this is latency)

  • Although split-transaction bus allows some overlap

• Make memory wider (assume monolithic memory)

  • Sending one address, yields transfer of more than one word if bus width allows it (e.g., Alpha 21064 has L2, DRAM, and memory bus all 256 bits wide)
  • But less modularity (buy bigger increments of memory)
  • Requires ECC on a word basis (or on the basis of the minimum write information unit). Otherwise need of “read-modify-write” when writes occur.

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