Main memory
Recall that on a cache miss, need to access memory. Takes 3 steps (e.g., for a read)
- Send the address
- Get the contents of the memory locations (at the DRAM level)
- Transfer the contents to the cache
DRAM parameters (memory latency at the DRAM level):
- Access time: time between the read is requested and the desired word arrives
- Cycle time: minimum time between requests to memory (cycle time > access time because need for stabilization of address lines)