Synthesis
Logic synthesis
- Compiler generates gates from combinational logic
- Optimizer minimizes logic
Sequential synthesis
- Compiler generates sequential logic
- Optimizer may minimize states
Register-transfer level (RTL) synthesis
- Can share logic elements (e.g. adders) via data flow
- You specify multiplexers to accomplish the share
Behavioral or high-level synthesis
- Tools figure out resource sharing (e.g. sharing adders)
- Tools derive finite-state machines