A few requirements for CSE467...

• Draw data-flow diagrams

  • Algorithm ? dataflow ? datapath and control
    • Then instance Verilog modules into Xilinx schematics

• Draw state diagrams

  • And do the state encoding
    • One-hot
      • Simplifies combinational logic (reduces # of inputs)
      • More CLBs for state, but less for logic
    • Output based ? use same bits for outputs and state
      • Don’t need CLBs to decode output from state

• Modularize your designs

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