Synthesis in CSE467

• FPGA Express synthesizes modules to gates

  • Combinational logic
  • Sequential logic

• Xilinx tools flatten and merge the gates

  • Minimizing combinational logic
  • Doesn’t minimize states in encoded FSMs

• Xilinx tools place and route the design

  • Assigning logic to CLBs
    • You get a timing report
    • You can apply constraints

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