Verilog case

• Without the default case, this would create a latch for Y

• Assigning X to a variable means synthesis is free to assign any value

// Simple binary encoder (input is 1-hot)

module encode (A, Y);

input [7:0] A; // 8-bit input vector

output [2:0] Y; // 3-bit encoded output

reg [2:0] Y; // target of assignment

always @(A)

case (A)

8’b00000001: Y = 0;

8’b00000010: Y = 1;

8’b00000100: Y = 2;

8’b00001000: Y = 3;

8’b00010000: Y = 4;

8’b00100000: Y = 5;

8’b01000000: Y = 6;

8’b10000000: Y = 7;

default: Y = 3’bX; // Don’t care when input is not 1-hot

endcase

endmodule

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