Verilog case (cont)

• Cases are executed sequentially

  • The following implements a priority encoder

// Priority encoder

module encode (A, Y);

input [7:0] A; // 8-bit input vector

output [2:0] Y; // 3-bit encoded output

reg [2:0] Y; // target of assignment

always @(A)

case (1’b1)

A[0]: Y = 0;

A[1]: Y = 1;

A[2]: Y = 2;

A[3]: Y = 3;

A[4]: Y = 4;

A[5]: Y = 5;

A[6]: Y = 6;

A[7]: Y = 7;

default: Y = 3’bX; // Don’t care when input is all 0’s

endcase

endmodule

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