Verilog case

• Sequential execution of cases

  • only first case that matches is executed (no break)
  • default case can be used

// Simple 4-1 mux

module mux4 (sel, A, B, C, D, Y);

input [1:0] sel; // 2-bit control signal

input A, B, C, D;

output Y;

reg Y; // target of assignment

always @(sel or A or B or C or D)

case (sel)

2’b00: Y = A;

2’b01: Y = B;

2’b10: Y = C;

2’b11: Y = D;

endcase

endmodule

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