Verilog if

• Another way

// Simple 4-1 mux

module mux4 (sel, A, B, C, D, Y);

input [1:0] sel; // 2-bit control signal

input A, B, C, D;

output Y;

reg Y; // target of assignment

always @(sel or A or B or C or D)

if (sel[0] == 0)

if (sel[1] == 0) Y = A;

else Y = B;

else

if (sel[1] == 0) Y = C;

else Y = D;

endmodule

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