Verilog if
Same as C if statement
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment
always @(sel or A or B or C or D)
if (sel == 2’b00) Y = A;
else if (sel == 2’b01) Y = B;
else if (sel == 2’b10) Y = C;
else if (sel == 2’b11) Y = D;
endmodule
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