CSE 378 Spring 2007

CSE Home

CSE 378 Spring 2007

About Us

Search

Contact Info

Home Administrative  Syllabus  Office Hours  Mailing List  Wiki Assignments  Reading  Homework  Labs  Exams Resources  Lecture Slides  Handouts  MIPS Resources  AHDL Resources Anonymous Feedback  Feedback Form

Memories This page describes the included Memory components. Memory is only useful if you can set its initial value, and that's not a trivial task. We wrote a script that make this process tractable, though not yet easy or enjoyable. The script asm_to_hex.pl should have been extracted with the lab archive. Module: BIOSROM256x32     In our single-cycle designs we don't need to write to the instruction memory, so this ROM allows us to write a program with up to 256 instructions. If the need for larger programs arises they can be tacked together, but that will make initializing the memory more complex. The actual implementation depends on the ovi_unisim library.      This component actually consists of 32 256x1 bit ROMs, 1 for each bit in the instruction. Each ROM has its own internal INIT parameter, and we have provided parameters INIT_C0 through INIT_C31 which are 256 bit hex values that init an entire ROM bit-slice.      Setting the ROM requires updating all of the INIT_C0 - INIT_C31 parameters appropriately. To make this possible we've written a script that takes an input in MIPS assembly and outputs the proper values for the individual INIT_Cn values. This will be done via the .ucf files that are provided. Each lab will have a provided script that will generate the required lines from a .s file. Check the individual lab pages for more information. Parameters:   Name Default Description INIT_FILE $DSN\src\bios.hex File to load to initialize the ROM. THIS DOES NOT INITIALIZE IT FOR IMPLEMENTATION. Port Description:   Name Dir Width Description ADDR In 8 Address to read from OUTPUT Out 31 Word stored at Address ADDR Symbol:   Notes:   There must be a glbl.GSR signal defined to use this component Module: Ram256x32_sw_ar_wb     This is the data memory you should use for Lab1. The reason is that it supports asynchronous reads (output changes when address changes).  This memory has only 256 words.  This means that only the lower 10 bits of your Address will be used.  It supports writing at the byte, half-word, and word level.  This is specified by the value of WE (2'b00 = don't write, 2'b01 = write bits [7:0] into correct byte, 2'10 = write word, 2'b11 = write half-word to upper or lower half. Parameters:   Name Default Description INIT 36'h0 The initial output value SRVAL 36'h0 The output value when SSR is set INIT_00-1F 256'h0 Initialization values. Not USED Port Description:   Name Dir Width Description CLK In 1 clock signal ADDR In 10 ADDR to read or write DI In 32 Data to write WE In 2 write signals: 2'b01 = write byte , 2'b10 = write word, 2'b11 = write half-word DO Out 32 Data read from memory Symbol:   Notes:   There must be a glbl.GSR signal defined to use this component Module: Memory_Toplevel     This module contains the entire memory system for the processor that you will be building. It contains a ROM that acts as the BIOS, asynchronous RAMs that act as Instruction Memory, Data Memory and stack space, and an IO controller that routes signals to and from the various IO devices on the processor. This module manages both instruction and data memory and fetches the appropriate instructions and data based on the addresses provided to it. The memory system contains 3 256 word RAMs each for the Instruction and Data memory and 1 256 word RAM for the stack. Initialization of this component can most easily be performed through use of the serial port and the bootloader. Memory space is mapped as follows: Instructions Addresses 0x00000000 - 0x000003FF: Instruction fetched from ROM Addresses 0x00400000 - 0x00400BFF: Instruction fetched from RAM Data Addresses 0x00400000 - 0x00400BFF - Data read/written to Instruction RAM. Only applicable if instructions are coming from the BIOS. Addresses 0x10000000 - 0x10000BFF - Data read/written to Data RAM Addresses 0x7FFF0000 - 0x7FFF03FF - Data read/written to Stack Addresses 0x80000000 - 0x800003FF - Data read/written to IO Device 1 Addresses 0x80000400 - 0x800007FF - Data read/written to IO Device 2 Addresses 0x80000800 - 0x80000BFF - Data read/written to IO Device 3 Addresses 0x80000C00 - 0x80000FFF - Data read/written to IO Device 4   Port Description:   Name Dir Width Description CLK In 1 clock signal WE In 2 write signals: WE[0] = WB, WE[1] = WW InstAddress In 32 The address of the instruction that should be fetched Data Address In 32 The address to read/write data to IODev1Input In 32 Data in from IO Device 1 IODev2Input In 32 Data in from IO Device 2 IODev3Input In 32 Data in from IO Device 3 IODev4Input In 32 Data in from IO Device 4 DataOut Out 32 Data read from memory Instruction Out 32 Instruction read from memory IODev1WE Out 2 WriteEnable signal for IO Device 1 IODev2WE Out 2 WriteEnable signal for IO Device 2 IODev3WE Out 2 WriteEnable signal for IO Device 3 IODev4WE Out 2 WriteEnable signal for IO Device 4   Symbol:     Module: CacheMemorySystem_4Word This module contains the required memory components for a cached processor to operate on. It is meant to be used in conjunction with an instruction cache, which is part of the library, and a data cache, which you will write. The memory system contains block RAMs for storage of instructions, data, and stack data. It also includes routing to up to four I/O devices based on the addresses provided. The memory system contains 3 16KB block RAMs each for the Instruction and Data memory and Stack. This memory system can be initialized through either the serial port and bootloader or the data2mem tool. Memory space is mapped as follows: Instructions Addresses 0x00000000 - 0x000003FF: Instruction fetched from ROM Addresses 0x00400000 - 0x00407FFF: Instruction fetched from RAM Data Addresses 0x00400000 - 0x00407FFF - Data read/written to Instruction RAM. Only applicable if instructions are coming from the BIOS. Addresses 0x10000000 - 0x10007FFF - Data read/written to Data RAM Addresses 0x7FFF0000 - 0x7FFF7FFF - Data read/written to Stack Addresses 0x80000000 - 0x800003FF - Data read/written to IO Device 1 Addresses 0x80000400 - 0x800007FF - Data read/written to IO Device 2 Addresses 0x80000800 - 0x80000BFF - Data read/written to IO Device 3 Addresses 0x80000C00 - 0x80000FFF - Data read/written to IO Device 4   Port Description:   Name Dir Width Description CLK In 1 clock signal Reset In 1 Resets the memory system. ICacheAddr In 28 The address of the instruction cache line that should be fetched from main memory ICacheReadRequest In 1 Signals memory to prepare a line for reading for the instruction cache. DCacheAddr In 28 The address of the data cache line that should be fetched from main memory DCacheDataIn In 128 4 word cache line to write to data memory. DCacheReadRequest In 1 Signals memory to prepare a line for reading for the data cache. DCacheWriteRequest In 1 Signals memory to write a line from the data cache to main memory. BypassAddress In 32 Address to send to the I/O devices. Determines which I/O device is accessed. BypassWrite In 2 Write Enable for I/O devices. Routed to the appropriate I/O device based on the address provided. BypassReadRequest In 1 Signals bypass controller to prepare for a read from I/O devices. IO_Dev0_DataIn In 32 Data in from IO Device 1 IO_Dev1_DataIn In 32 Data in from IO Device 2 IO_Dev2_DataIn In 32 Data in from IO Device 3 IO_Dev3_DataIn In 32 Data in from IO Device 4 DCacheDataOut Out 128 4 word line of data read from memory for the data cache DCacheValid Out 1 Signals that the data from main memory is ready to be read by the data cache or that data has been written successfully DCacheInvalidAddress Out 1 Signals that an invalid memory address was provided as a request for data. ICacheDataOut Out 128 4 word line of instructions read from memory for the instruction cache ICacheValid Out 1 Signals that the data from main memory is ready to be read by the instruction cache ICacheInvalidAddress Out 1 Signals that an invalid memory address was provided as a request for instructions. BypassDataOut Out 32 Data from I/O Devices that bypasses the caches. BypassInvalidAddress Out 1 Signals that an invalid memory address was provided as a request to the bypass. IO_Dev0_WE Out 2 Write Enable signal for IO Device 1 IO_Dev1_WE Out 2 Write Enable signal for IO Device 2 IO_Dev2_WE Out 2 Write Enable signal for IO Device 3 IO_Dev3_WE Out 2 Write Enable signal for IO Device 4 IO_VGAChar_WE Out 2 Write Enable signal for the VGA Character Plane IO_VGAColor_WE Out 2 Write Enable signal for VGA Color Plane   Symbol:

	Computer Science & Engineering University of Washington Box 352350 Seattle, WA  98195-2350 (206) 543-1695 voice, (206) 543-2969 FAX [comments to Course Staff]