378 Spring 2007
Computer Organization and Assembly Programming
Contact info:
	Mark Oskin, oskin@cs.washington.edu, AIM: bigarchkahuna
	Shen-Hui Lee, shen@cs.washington.edu
	Dana Fujimoto, cuteness@cs.washington.edu
	Roger Wong, shren@cs.washington.edu
	All of us at once: cse378-tas@cs.washington.edu
	The entire class: cse378@cs.washington.edu
Book:		Patterson and Hennessy, Computer Organization.  A Note about international 	editions: generally, purchasing and using the international version of this book is fine for this class (I hear in Singapore it’s only $12).  Homework assignments are given by the US edition, however, and the numbering for problems is different between the international and domestic editions.  Furthermore, the domestic edition contains a helpful green card in the front.  This green card will be your best friend in the lab.   International editions contain the same card, but on thin paper.  Nevertheless, its your money so its up to you.
Grading:	60% Lab, 10% Homework / Class participation, 15% midterm, 15% final
Due dates:	All due dates are at 5pm on the date stated.
Late policy:	Any thing (except the midterm & final) can be turned in 1 day late for any reason.  The only requirement is that you email Shen, Dana or Roger (not Mark!) ON OR BEFORE the original due date.  No fancy excuse is required, just tell us you are going to be late.  In the quarter you get 1 special super-late 1 week extension.  To use it, you must email cse378@cs a song parody of an 80’s era big-hair band song.  The parody must be new and original, your own work, and funny.
Homework:	There are 3-5 homework assignments in this class.  The first 2-3 are programming assignments.  They consist of programming some small functions in MIPS assembly.  You write these using some text editor, and then simulate them using a program called “SPIM”.  You can download your own copy of SPIM and install it on your computers, or use the one pre-installed on the department machines.  There will be a couple book work assignments for good measure.  The last programming assignment will be to write a cache/TLB simulator.  You can write this in any high-level language of your choice.
Labs:  This class has a substantial lab component.  It is the majority of your grade in this class.  There are 4 labs.  Each lab will require two weeks to finish.  DO NOT WAIT UNTIL THE SECOND WEEK TO START THE LAB.  THEY ARE TIME CONSUMING.  These labs will walk you through the design and construction of a pipelined MIPS processor.  When you finish these labs you will have designed a fully working MIPS processor, capable of executing arbitrary C code, and one that runs on real hardware inside of an FPGA.  It’ll be fun, trust me.  You should work on the lab in pairs.  While you can work alone on it, given  the substantial time commitment required, I highly recommend you work with a partner.
Exams:  There will be a midterm and a final.  I expect that if you attend class, keep up with reading, and are doing well in the lab, then the midterm / final will not require any studying or stress.
Class Wiki: A wiki has been set up for this class in order to facilitate communication between students and to give you a place to note down any interesting discoveries or problems that you have run into while working on the labs or assignments so that others can benefit from your experiences. The wiki also contains wikified versions of the labs and assignments that you can edit if you feel that something is unclear about them. We will review modifications to the assignments and transfer them back to the actual pages if they are helpful. The wiki can be accessed through the Wiki link on the course website. Constructive participation on the wiki will count towards your class participation score.
Cheating:  Don’t go there; it’ll end your academic career.
Topics:
•	basic computer organization
•	CPU, memory, I/O, multi-core
•	representation of data
•	how a program is compiled and executed
•	performance metrics for computer systems
•	execution time, CPI
•	MIPS, MFLOPS
•	instruction set design
•	registers
•	arithmetic-logical instructions
•	load-store instructions and operand addressing
•	flow of control instructions
•	instruction encoding
•	instruction formats
•	RISC vs. CISC
•	interface with the compiler
•	user stack
•	procedure call conventions
•	processor implementation
•	   datapath/control
•	pipelining
•	ideal pipeline
•	data hazards & forwarding
•	control hazards & branch prediction
•	instruction-level parallelism
•	memory hierarchy
•	   caches
•	   cache organizations
•	   performance metrics for caches, taxonomy of cache misses
•	   parameters for cache design
•	   write strategies
•	exceptions/interrupts (interaction with operating system)