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Caches
Module: ICache_4Word
This is an instruction cache with one 4 word line designed to be used in a pipelined processor with caching. The cache operates by sending a request to memory, then waiting for the main memory to respond that it has completed the request before moving on. To prevent this cache and the data cache from accessing memory at the same time, this cache is capable of stalling the entire pipeline while it reads from memory.
Port Description:
|
| |
| Name |
Dir |
Width |
Description |
CLK |
In |
1 |
Clock signal for the cache, should be the same as the processor clock. |
CacheInvalidAddress |
In |
1 |
Signals the cache if the address requested is invalid. Not currently in use. |
CacheLine |
In |
128 |
Data requested from memory |
CacheValid |
In |
1 |
Signal from memory to indicate data provided is now valid |
InstrAddr |
In |
32 |
The address of the instruction requested by the processor |
Reset |
In |
1 |
Resets the cache |
CacheAddress |
Out |
28 |
Address of data requested from memory |
CacheReadRequest |
Out |
1 |
Notifies memory that the cache is requesting data |
Instruction |
Out |
32 |
The current instruction as specified by the InstrAddr value |
InvalidAddress |
Out |
1 |
Signal by the cache that it has received an invalid address |
Stall |
Out |
1 |
Signal to the processor to stall while the cache is fetching data. |
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Module: ICache_1Word
This is an instruction cache with one 1 word line designed to be used in a pipelined processor with caching. The cache operates by sending a request to memory, then waiting for the main memory to respond that it has completed the request before moving on. To prevent this cache and the data cache from accessing memory at the same time, this cache is capable of stalling the entire pipeline while it reads from memory.
Port Description:
|
| |
| Name |
Dir |
Width |
Description |
CLK |
In |
1 |
Clock signal for the cache, should be the same as the processor clock. |
CacheInvalidAddress |
In |
1 |
Signals the cache if the address requested is invalid. Not currently in use. |
CacheLine |
In |
32 |
Data requested from memory |
CacheValid |
In |
1 |
Signal from memory to indicate data provided is now valid |
InstrAddr |
In |
32 |
The address of the instruction requested by the processor |
Reset |
In |
1 |
Resets the cache |
CacheAddress |
Out |
28 |
Address of data requested from memory |
CacheReadRequest |
Out |
1 |
Notifies memory that the cache is requesting data |
Instruction |
Out |
32 |
The current instruction as specified by the InstrAddr value |
InvalidAddress |
Out |
1 |
Signal by the cache that it has received an invalid address |
Stall |
Out |
1 |
Signal to the processor to stall while the cache is fetching data. |
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