CSE370 Assignments

Assignment Date Distributed Date Due Annotated Solutions
Assignment 1  9/27/99 10/4/99 Solution 1 
Assignment 2 (pdf) 

Design Works Example in PowerPoint

10/4/99 10/11/99 Solution 2

Design Works Files for Question 3a(Circuit)

Design Works Files for Question 3a (Timings)

Design Works Files for Question 4 (Ciruit)

Assignment 3 10/11/99 10/18/99 Solution 3

Design Works Circuit for Question 1

Assignment 4 PDF or Web 10/18/99 10/27/99

Solution 4 in HTML

Solution 4 question 4 in DesignWorks

Assignment 5 PDF or Web 11/1/99 11/8/99 Solution 5

Design Works Files for Part D

Design Works Library for part D

 Assignment 6 PDF or Web

Verilog Example for Design Works

11/8/99 11/15/99 Solution 6 in HTML  or PDF

Design File  and Timing File

 Assingment 7 in PDF or Web  11/17/99 11/24/99 Solution 7 in PDF 
 Assignment 8 in PDF or Web

ALU with SHR modification

ALU with SHR w/ bug fixes (shifting and F7 port direction)

Verilog File for Decoder inside ALUDP in above DW file

Tester DW file with Verilog File

Note: Verilog files included for reference. You should be able to use the tester and the ALU without reloading the Verilog into Design Works

11/23/99 12/9/99


DW Solution to Problem 4 

PDF Solutions to Problems 1-3

Corrected PDF Solution to Problem 2

HTML Solution to Problem 4

PDF Solution to Problem 4


Comments to: cse370-webmaster@cs.washington.edu (Last Update: 12/13/99 )