Homework 6 solutions

The Table

Opcode Xi Yi Zi C0 Fi Ci+1 N C Z V
ADD Ai Bi Ci 0 Si Zi+1 F7 C8 nor(F0..F7) C8xorX7
INC Ai 0 Ci 1 Si Zi+1 F7 C8 nor(F0..F7) C8xorX7
DEC Ai 1 Ci 0 Si Zi+1 F7 C8 nor(F0..F7) C8xorX7
SUB Ai ~Bi Ci 1 Si Zi+1 F7 C8 nor(F0..F7) C8xorX7
CMP Ai ~Bi Ci 1 Si Zi+1 F7 C8 nor(F0..F7) C8xorX7
PASS Ai 0 0 x Si x F7 C8/0 nor(F0..F7) C8xorX7/0
NEG ~Ai 0 Ci 1 Si Zi+1 F7 x nor(F0..F7) C8xorX7
XOR Ai Bi 0 x Si x F7 0 nor(F0..F7) 0
XNOR Ai ~Bi 0 x Si x F7 0 nor(F0..F7) 0
NOT ~Ai 0 0 x Si x F7 0 nor(F0..F7) 0
AND Ai Bi 0 x Zi+1 x F7 0 nor(F0..F7) 0
OR Ai Bi 1 x Zi+1 x F7 0 nor(F0..F7) 0
SHL x x x x Ai-1 x F7 A7 nor(F0..F7) 0
SHR x x x x Ai+1 x F7 0 nor(F0..F7) 0

Design Notes

Control Line Definitions:

Gate Level Implementation of an ALU BitSlice: Total Gates = 13 + (4:1mux) + Inverter-for-Bi = 18gates

Remainder of System:

Condition Codes

Control Logic: By inspecting the table above. The following control lines are asserted for the following instructions

Optimizing the Control Logic: Determine encoding by placing the the instructions in a K-MAP while trying to keep the groups together according to the above. For example, NEG and NOT are close together to make s0 simple, ADD and DEC are adjacent to make s9 simple, s1 and s2 are grouped as good as can be without violating the separation between logic and arithmetic functions, etc. This is probably not an optimal placement, but its not bad.

P3P2P1P0 00 01 11 10
00 OR PASS INC x
01 AND NOT NEG x
11 SHR XNOR DEC ADD
10 SHL XOR CMP SUB

Letting ARITHMETIC = P3, we organize the k-map so that all arithmetic functions are in the P3=1 region. According to the K-MAP we get the following logic functions. All but s1 and s2 can be implement with one gate or less.

Decoder Gate Count =  12 + (4 inversions) = 16

Total System = (BitSlice*8) + (CC) + (Decoder) + (2 control line inversions) = 144 + 6 + 16  + 2 = 168 gates

The critical delay is as follows:

The total delay = 11 + (6*6) + 6 = 53 gate delays

Here is the Verilog Model for the Controller:

module Decoder(P3, P2, P1, P0, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);

    input P3;

    input P2;

    input P1;

    input P0;

    output s0;

    output s1;

    output s2;

    output s3;

    output s4;

    output s5;

    output s6;

    output s7;

    output s8;

    output s9;

    assign s7 =  P3;

    assign s8 = ~P3 & ~P2 & P1 & ~P0;

    assign s3 = ~P2 & ~P1 & ~P0;

    assign s9 = ~(P3 & P1 & P0);

    assign s4 = ~P3;

    assign s5 = ~P3 & ~P2 & P1;

    assign s6 = ~P3 & ~P2 & ~s8;

    assign s0 =  P2 & ~P1 & P0;

    assign s1 =  (P2 & ~P1) | (P3 & P2 & P0);

    assign s2 =  (P2 & P1 & P0) | (P3 & P1 & ~P0);

endmodule

 

ALU Schematic

Test Vectors

 

Top Level Schematic