module Test(a0, a1, a2, a3, a4, f0, f1, f2, f3, f4);
  input		a0;  // DW only supports single bit inputs and outputs
  input		a1;
  input		a2;
  input		a3;
  input		a4;
  output	f0;
  output	f1;
  output	f2;
  output	f3;
  output	f4;
  reg           f0;
  reg           f1;
  reg           f2;
  reg           f3;
  reg           f4;

  reg  [4:0]    tempf;
  reg  [4:0]    tempa;

  assign        tempa = {a0,a1,a2,a3,a4};  // convert single bit inputs to a "word"
  assign        f0 = tempf[0];
  assign        f1 = tempf[1];
  assign        f2 = tempf[2];
  assign        f3 = tempf[3];
  assign        f4 = tempf[4];

  always @(tempa) begin
         // example using tempa, tempf as 5 bit numbers
         tempf = tempa+1;
	 // examples using only parts of tempa, tempf
         tempf[1:0] = tempa[4:3] & tempa[2:1];
         tempf[4]   = tempa[0];         
  end


endmodule