# Course Calendar     CSE 370   Spring 2003

This is the schedule of lectures, related readings, and homework and exam dates. Last revised 5/29/03.

You can expect a homework assignment every week. Assignments will typically be handed out on Wednesday in class, and due the following Friday at the beginning of class. We may ask you to submit assignments done using the CAD Tools (Active-HDL) electronically. We will give you instructions on how to do this.

The last column indicates the pages of the textbook that are relevant to the lecture material. It is an excellent idea to read over this before it is covered in class. The textbook is also a good source of additional explanations and examples.
 Week Day Date Topic Textbook reading #1 M 3/31 Introduction and Course Overview pp. 1-15 W 4/2 Binary numbers, Boolean algebra Assignment #1 distributed pp. 229-254 F 4/4 Boolean algebra and theorems, gates pp. 17-34 #2 M 4/7 Basic electronics Logic gates pp. 35-48; 67-86 W 4/9 de Morgan's Theorem; Canonical forms Assignment #2 distributed pp. 149-165 F 4/11 Karnaugh Maps/Logic minimization Assignment #1 due; Quiz 1 pp. 149-165 #3 M 4/14 Kmap examples Multilevel logic pp. 166-183 W 4/16 HDLs Assignment #3 distributed pp. 184-207 F 4/18 more on Verilog Assignment #2 due #4 M 4/21 Timing Diagrams, Hazards Combinational Verilog pp. 48-60; Appendix A W 4/23 Special Topics F 4/25 No class; Engineering Open House #5 M 4/28 Multiplexers; Demultiplexers Assignment #3 due pp. 297-315 W 4/30 PLDs Assignment #4 distributed;  Quiz 2 pp. 87-102 F 5/2 PLDs: PLAs, PALs, ROMs pp. 87-102 #6 M 5/5 Adders; carry lookahead; ALUs pp. 255-288 W 5/7 Introduction to Sequential Logic Sequential logic: registers and clocks Assignment #5 distributed notes F 5/9 Flip-flops & registers; Metastability Assignment #4 due pp. 349-358 #7 M 5/12 Sequential Verilog pp. 359-368 W 5/14 Cascading flip-flops; Clock skew; Counters Assignment #6 distributed pp. 369-370 F 5/16 Finite-state machines Assignment #5 due;  Quiz 3 pp. 371-385 #8 M 5/19 Counter design; Self-starting counters pp. 400-434 W 5/21 Moore vs. Mealy Assignment #7 distributed pp. 446-467 F 5/23 More  FSM; vending machine Assignment #6 due pp. 400-434 #9 M 5/26 Memorial Day-- no class W 5/28 Ant Brain design Assignment #8 distributed pp. 467-477 F 5/30 More Examples Assignment #7 due;  Quiz 4 #10 M 6/2 State Encoding; One-hot encoding pp. 584-599 W 6/4 Optimizing FSMs; Retiming pp. 458-462 F 6/6 Summary, Review Assignment #8 due M-2:30- 4:20pm 6/9 Final Exam