Week 
Day 
Date 
Topic 
Textbook
reading 
#1 
M 
3/31 
Introduction and Course Overview 
pp. 115


W 
4/2 
Binary numbers, Boolean algebra
Assignment #1 distributed

pp. 229254 

F 
4/4 
Boolean algebra and theorems, gates 
pp. 1734

#2 
M 
4/7

Basic
electronics
Logic gates 
pp. 3548; 6786 

W 
4/9 
de
Morgan's Theorem; Canonical forms
Assignment #2 distributed

pp. 149165 

F 
4/11

Karnaugh
Maps/Logic minimization
Assignment #1 due; Quiz 1 
pp. 149165 
#3

M

4/14

Kmap examples
Multilevel logic 
pp. 166183 

W

4/16

HDLs
Assignment #3 distributed

pp. 184207 

F

4/18

more on Verilog
Assignment #2 due


#4

M

4/21

Timing Diagrams,
Hazards
Combinational Verilog 
pp. 4860; Appendix A


W

4/23

Special Topics



F

4/25

No class; Engineering Open House


#5

M

4/28

Multiplexers;
Demultiplexers
Assignment #3 due 
pp. 297315 

W

4/30

PLDs
Assignment #4
distributed; Quiz 2 
pp. 87102 

F

5/2 
PLDs: PLAs, PALs,
ROMs 
pp. 87102 
#6

M

5/5 
Adders; carry
lookahead; ALUs 
pp. 255288 

W

5/7 
Introduction to
Sequential Logic
Sequential
logic: registers and clocks
Assignment #5
distributed

notes 

F

5/9 
Flipflops &
registers; Metastability
Assignment #4 due 
pp. 349358 
#7

M

5/12 
Sequential Verilog

pp. 359368 

W

5/14 
Cascading
flipflops; Clock skew; Counters
Assignment #6
distributed

pp. 369370 

F

5/16 
Finitestate machines
Assignment
#5 due; Quiz 3 
pp. 371385 
#8

M

5/19 
Counter design;
Selfstarting counters 
pp. 400434 

W

5/21 
Moore vs. Mealy
Assignment #7
distributed

pp. 446467 

F

5/23 
More FSM;
vending machine
Assignment #6 due 
pp. 400434 
#9

M

5/26 
Memorial Day no class



W

5/28 
Ant Brain design
Assignment #8
distributed

pp. 467477 

F

5/30 
More Examples
Assignment #7 due; Quiz
4 

#10

M

6/2 
State Encoding;
Onehot encoding 
pp. 584599 

W

6/4

Optimizing FSMs;
Retiming

pp. 458462 

F

6/6

Summary, Review
Assignment
#8 due








M2:30
4:20pm

6/9

Final Exam

