CS 370 - Spring
2003 Introduction to Digital Design
Instructor: Bruce Hemingway
Homework Set 3
DUE: Due start of class, Monday, April 28
Collaboration Policy: See homework 1.
Late Homework Policy: See homework 1.
Please show all of your work.Your solutions must be
legible…we will not spend time trying to decipher poorly written
assignments.
I. Draw a K-map to do the following:
- 1. Brown 4.6 p. 221
- 2. Brown 4.7 p. 221
II. Go through the Active-HDL CAD Tools : Tutorial #2, Heirarchical Designs,
and Tutorial #3, Verilog Modules, in order to do 3-6 below.
Then use Active-HDL to do the
following:
- 3. Brown 2.39 p. 64
- 4. Brown 2.40 p. 64
- 5. Brown 4.41 p. 224
- 6. Brown 4.42 p. 225
Hand in print-outs of your Verilog code.