CSEP 548 - Spring 2003

This course will cover the architecture of the single-chip microprocessor: instruction set design and processor implementation (pipelining, multiple issue, speculative execution). Memory hierarchy: on-chip and off-chip caches, TLB's and thei r management, virtual memory from the hardware viewpoint. I/O devices and control: buses, disks and RAIDs. Shared-memory multiprocessors and cache coherence.

Instructor:
   Susan Eggers
   eggers@cs
   Office: 315 Sieg Hall
   Office Hours by appointment

TA:
   Evan Welbourne
   evan@cs
   Office: 226a Sieg Hall
   Office Hours by appointment


- (4/2/04):	For those of you who do not have CS accounts and so are unable to subscribe to the mailing lists or log in to the instructional machines, please fill out a CS account application form and get it to support (Sieg 230).
- (4/2/03):	The Blis simulator which we will be using, and its documentation can be found at http://www.cs.washington.edu/homes/oskin/Bliss/
- (4/2/03):	For information and options on logging in to CSE instructional machines from home or work, please refer to the following links: http://www.cs.washington.edu/lab/remote-access/ http://www.washington.edu/computing/software/uwick/teraterm/ http://www.washington.edu/computing/software/uwick/ You could also go to support (230 Sieg) in person and check-out a copy of the Windows-compatible X-client "Reflection X"
- (3/31/03):	Please subscribe to the course mailing lists: Subscribe via the web: subscribe to csep548@cs, and subscribe to csep548-discuss@cs OR Send an email with "subscribe" as the subject to: csep548-request@cs.washington.edu and csep548-discuss-request@cs.washington.edu
- (3/31/03):	Our textbook is "Computer Architecture, A Quantitative Approach, 3rd ed." by John L. Hennessy and David Patterson, published by Morgan Kaufmann (see cover to the right).
- (3/31/03):	The undergraduate version of our textbook is "Computer Organization and Design: The Hardware/Software Interface", also by Hennessy and Patterson.

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