MIPS R10000 pipelines

• MIPS R10000

  • 5 pipelines
  • Common first 2 stages (IF, ID)
  • 2 Integer ALU’s with 3 more stages (one ALU used for compares; apparently 3 cycles branch taken penalty but the resume buffer reduces it to 2)
  • 1 Load-store with 4 more stages (1 cycle load delay)
  • 2 FP units with 5 more stages, 1 for Add, 1 for Mpy and long latency ops such as Div and Sqrt)

• Can issue 4 instructions at a time (4-way issue)

• Out-of-order execution with register renaming (see later)

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