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IF

ID

RF

RF

RF

EX

Addr

EX1 EX2 EX3

Mem

WB

WB

WB

2 int ALU’s

1 load/store

1 FP add

1 FP mpy

These two stages are quite complex. There is also some mechanism not shown in the picture associated with WB

Load delay 1 cycle

Mispredicted taken branch 2 cycles penalty (resume buffer)

Mispredicted not taken branch 3 cycles penalty

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