Branch and load delays

• Branch completion at end of EX

  • Hence branch delay 3 cycles (PC selection at IF)

• Load delay

  • Assuming a cache hit, data is ready at end of DS
  • If needed for next instruction (beg of EX) needs two bubbles

• Another complexity: conflict in WB stage

  • Both the floating-point pipeline and the integer pipeline which performs the loads might want to access the WB stage for floating-point registers at the same time (structural hazard). We’ll see how to resolve this soon.

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